Formal design specification of a Processor Interface Unit

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society

Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port

Towards the formal specification of the requirements and design of a processor interface unit

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.

Towards the formal verification of the requirements and design of a processor interface unit

The formal verification of the design and partial requirements for a Processor Interface Unit (PIU) using the Higher Order Logic (HOL) theorem-proving system is described. The processor interface unit is a single-chip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. It provides the opportunity to investigate the specification and verification of a real-world subsystem within a commercially-developed fault-tolerant computer. An overview of the PIU verification effort is given. The actual HOL listing from the verification effort are documented in a companion NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings' including the general-purpose HOL theories and definitions that support the PIU verification as well as tactics used in the proofs

Landau-Zener Problem for Trilinear Hamiltonians

We consider a nonlinear version of the Landau-Zener problem, focusing on photoassociation of a Bose-Einstein condensate as a specific example. Contrary to the exponential rate dependence obtained for the linear problem, a series expansion technique indicates that, when the resonance is crossed slowly, the probability for failure of adiabaticity is directly proportional to the rate at which the resonance is crossed.Comment: 4.5 pages, 1 figure, transferred to PRA; v2 adds discussion, clarification, and explicit numbers for Na and 87R

Monolithic Flexure Pre-Stressed Ultrasonic Horns

A monolithic ultrasonic horn where the horn, backing, and pre-stress structures are combined in a single monolithic piece is disclosed. Pre-stress is applied by external flexure structures. The provision of the external flexures has numerous advantages including the elimination of the need for a pre-stress bolt. The removal of the pre-stress bolt eliminates potential internal electric discharge points in the actuator. In addition, it reduces the chances of mechanical failure in the actuator stacks that result from the free surface in the hole of conventional ring stacks. In addition, the removal of the stress bolt and the corresponding reduction in the overall number of parts reduces the overall complexity of the resulting ultrasonic horn actuator and simplifies the ease of the design, fabrication and integration of the actuator of the present invention into other structures

Monolithic Flexure Pre-Stressed Ultrasonic Horns

A monolithic ultrasonic horn where the horn, backing, and pre-stress structures are combined in a single monolithic piece is disclosed. Pre-stress is applied by external flexure structures. The provision of the external flexures has numerous advantages including the elimination of the need for a pre-stress bolt. The removal of the pre-stress bolt eliminates potential internal electric discharge points in the actuator. In addition, it reduces the chances of mechanical failure in the actuator stacks that result from the free surface in the hole of conventional ring stacks. In addition, the removal of the stress bolt and the corresponding reduction in the overall number of parts reduces the overall complexity of the resulting ultrasonic horn actuator and simplifies the ease of the design, fabrication and integration of the actuator of the present invention into other structures