65 research outputs found

    A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology

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    A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving metal gate granularity and line-edge roughness as the two major random variation sources. The variations of Vth induced by these two major categories are theoretically decomposed based on the distinction in physical mechanisms and their influences on different electrical characteristics. The effectiveness of the proposed method is confirmed through both TCAD simulations and experimental results. This letter can provide helpful guidelines for variation-aware technology development

    Impact of self-heating on the statistical variability in bulk and SOI FinFETs

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    In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

    Decoupled Local Aggregation for Point Cloud Learning

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    The unstructured nature of point clouds demands that local aggregation be adaptive to different local structures. Previous methods meet this by explicitly embedding spatial relations into each aggregation process. Although this coupled approach has been shown effective in generating clear semantics, aggregation can be greatly slowed down due to repeated relation learning and redundant computation to mix directional and point features. In this work, we propose to decouple the explicit modelling of spatial relations from local aggregation. We theoretically prove that basic neighbor pooling operations can too function without loss of clarity in feature fusion, so long as essential spatial information has been encoded in point features. As an instantiation of decoupled local aggregation, we present DeLA, a lightweight point network, where in each learning stage relative spatial encodings are first formed, and only pointwise convolutions plus edge max-pooling are used for local aggregation then. Further, a regularization term is employed to reduce potential ambiguity through the prediction of relative coordinates. Conceptually simple though, experimental results on five classic benchmarks demonstrate that DeLA achieves state-of-the-art performance with reduced or comparable latency. Specifically, DeLA achieves over 90\% overall accuracy on ScanObjectNN and 74\% mIoU on S3DIS Area 5. Our code is available at https://github.com/Matrix-ASC/DeLA

    Back-gate bias dependence of the statistical variability of FDSOI MOSFETs with thin BOX

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    The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D 'atomistic' drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on-current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications. © 1963-2012 IEEE.published_or_final_versio

    Simulation Based DC and Dynamic Behaviour Characterization of Z2FET

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    This work presents a TCAD investigation of the operation of a Z2FET device for memory application, where the TCAD model is well calibrated to experimental hysteresis curves. The DC operation of the Z2FET has been analyzed for 4 cases, based on the permutations of the front and back gate biases, to identify and compare different modes of operation. The memory mode of operation is under the “Thyristor” like scenario with positive and negative biases applied to the front and back gates respectively. The dynamic property of Z2FET as a memory device is shown and its operation mechanism is described

    Investigation on the amplitude of random telegraph noise (RTN) in nanoscale MOSFETs: Scaling limit of “Hole in the inversion layer” model

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    In this paper, the widely adopted “hole in the inversion layer” (HIL) model for predicting the amplitude of random telegraph noise (RTN) in nanoscale MOSFETs, is theoretically revisited with focusing on its scaling limit and validation range. It is found that this simple physical model fail to apply on ultra-scaled devices with L<;20nm and/or W<;10nm, due to the non-negligible impact from source/drain and the failure of assumed equivalence to resistor network in ultra-scaled devices. This work provides a deeper understanding to this model and is helpful for accurate prediction of RTN amplitude in nanoscale devices and circuits

    Simulation study of the impact of quantum confinement on the electrostatically driven oerformance of n-type nanowire transistors

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    In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions

    Carbon-emcoating architecture boosts lithium storage of Nb2O5

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    Intercalation transition metal oxides (ITMO) have attracted great attention as lithium-ion battery negative electrodes due to high operation safety, high capacity and rapid ion intercalation. However, the intrinsic low electron conductivity plagues the lifetime and cell performance of the ITMO negative electrode. Here we design a new carbon-emcoating architecture through single CO2 activation treatment as demonstrated by the Nb2O5/C nanohybrid. Triple structure engineering of the carbon-emcoating Nb2O5/C nanohybrid is achieved in terms of porosity, composition, and crystallographic phase. The carbon-embedding Nb2O5/C nanohybrids show superior cycling and rate performance compared with the conventional carbon coating, with reversible capacity of 387 mA h g−1 at 0.2 C and 92% of capacity retained after 500 cycles at 1 C. Differential electrochemical mass spectrometry (DEMS) indicates that the carbon emcoated Nb2O5 nanohybrids present less gas evolution than commercial lithium titanate oxide during cycling. The unique carbon-emcoating technique can be universally applied to other ITMO negative electrodes to achieve high electrochemical performance
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