Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices

Four-gate transistor analog multiplier circuit

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed

Universal programmable logic gate and routing method

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic

Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design

G4-FET Based Voltage Reference

A precise and stable voltage reference is essential to analog/mixed-signal SoC (system-on-a-chip) applications. The most commonly used voltage reference in standard CMOS processes, the bandgap voltage reference, is limited due to output drift in wide temperature range applications. The temperature drift associated with the bandgap voltage reference is non-linear, thus temperature compensation is difficult. A new reference circuit, the JFET-based voltage reference, is proven to be more temperature stable. However, the JFET-based voltage reference requires a specialized Bi-CMOS process with additional fabrication steps to alter the channel doping for selected devices. The purpose of this thesis is to investigate the feasibility of the JFET-based voltage reference circuit topology in a CMOS-compatible process. The novel G4-FET device fabricated on a standard PDSOI (partially-depleted silicon-on-insulator) CMOS process is chosen as an alternative to the JFET device. A theoretical development of the G4-FET is summarized and results of device characterization are presented. Based on device characterization, all four gates of the G4-FET device are exploited to achieve an equivalent circuit operation without requiring any additional process steps. Results from this characterization are used to design an improved voltage reference based on G4-FETs and test results from a prototype reference circuit are shown including output temperature coefficient, output noise, and power supply rejection. The output voltage achieves approximately constant output variation with temperature over the temperature range of −5 °C to 85 °C, implying that the circuit may be readily temperature compensated, in this case by an inverse-PTAT (proportional-to-absolute-temperature) current. Finally, suggestions for improved reference performance and fully monolithic compatibility are given

Highly active and stable single iron site confined in graphene nanosheets for oxygen reduction reaction

Exploring high performance non-precious metal catalysts to substitute Pt for oxygen reduction reaction (ORR) has stimulated wide research interest recently, but it remains a great challenge. Herein, we report a single iron site confined in graphene catalyst via 4N atoms, forming flat FeN4 structure in the matrix of graphene. The optimized catalyst shows a high ORR activity, almost coming up to the activity of commercial 40% Pt/C catalyst, but a significantly higher stability and tolerance to SOx, NOx and methanol with respect to 40% Pt/C. This well-defined structure provides an ideal model to study the catalytic origin of iron-based catalysts. DFT calculations indicate that the high ORR activity origins from highly dispersed and high-density coordinatively unsaturated Fe centers, and the excellent stability origins from the unique confinement of the graphene matrix via 4N atoms. This reaction can proceed easily to H2O via a four electron transfer path way on the single iron site, which is further confirmed by the experiment. This experimental and theoretical study provides a further insight into the nature of the Fe/N/C catalyst and also introduces a reference for designing high efficient catalysts in electrocatalysis

SiGe BiCMOS Precision Voltage References for Extreme Temperature Range Electronics

Abstract — We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 oC to-180 oC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to-180 oC. Our best case reference achieves a 28.1 ppm / oC temperature coefficient over +27 oC to-180 oC, more than adequate for the intended lunar electronics applications. Index Terms — analog circuits, SiGe HBT, cryogenic temperature, voltage reference, device physics