A Clock and Data Recovery Circuit for Optical Communications in 0.18 m CMOS

The amount of data transmitted over the global communications networks has experienced a dramatic increase over the last years, mainly driven by the exponential growth of the Internet. For this reason, increasingly faster and more reliable circuits are needed to allow a correct performance at speeds in the range of the Gbps. The superior power characteristics and overall performance make optical fiber the preferred choice to implement the channel in communications links, giving rise to the concept of optical communications. Due to their bandwidth limitations, in a typical optical communcations link data cannot be transmitted with a timing reference; the clock signal that allows its correct interpretation has to be extracted at the receiver in a block called clock and data recovery circuit (CDR). Typically, a CDR circuit is a closed-loop system that generates an oscillating signal capable of tracking the phase of the incoming data stream; as well, it uses the generated clock signal to regenerate the data stream, minimising the effects of non-idealities during transmission. This paper presents the design of a CDR circuit intended to meet the 10GBase-LX4 Ethernet specifications for continuous operation at 3.125 GHz, designed in a standard 0.18 m CMOS technology provided by UMC. A detailed description of the full CDR circuit and the different blocks taking part in it will be provided, emphasising the requirements that each of them must satisfy. Finally, the correct performance of the proposed CDR circuit will be analysed by means of an extensive set of post-layout simulations

CMOS Receiver Front-End Architecture for High-Speed SI-POF Links

This works presents a new CMOS analog front-end for short-reach high-speed optical communications which compensates the limited bandwidth of POF channels and is suitable for the required large area photodetectorf The proposed pseudo-differential architecture, formed by a preamplifier and an equalizer, has been designed in a standard 0.18-μm CMOS process with a 1-V supply voltage targeting gigabit transmission for NRZ modulation. The preamplifier is based on the flipped voltage follower stage to attain a very low input resistance in order to handle the large phodiode capacitance (3 pF). The equalizer can adjust the high-frequency boosting and the gain, to compensate for the variation of the characteristics of the channel due to length of the fiber, connections, etc. causing subtantial changes of the fiber bandwidth. Reliable electrical models are employed for a Mitsubishi GH SI-POF with 10-m to 50-m length and for a S5972 silicon photodiode from Hamamatsu suitable for such a fiber due to its large diameter (0.8 mm) and responsivity at 650 nm (0.44A/W). The bandwidth of the received signal can be enhanced from 100 MHz to 1.4 GHz and from 300 MHz to 1.4 GHz for a 50-m and 10-m POF respectively. The proposed circuit shows a transimpedance of 41.5 dBΩ while the theoretical sensitivity from noise performance is below -7.5 dBm with a BER = 10-12. The power consumption is below 16 mW from 1-V supply voltage. In conclusion it targets 1.25 Gbps through a 1-mm SI-POF up to 50-m length with a commercial Si PIN photodiode

The Social Network of Contemporary Popular Musicians

In this paper we analyze two social network datasets of contemporary musicians constructed from allmusic.com (AMG), a music and artists' information database: one is the collaboration network in which two musicians are connected if they have performed in or produced an album together, and the other is the similarity network in which they are connected if they where musically similar according to music experts. We find that, while both networks exhibit typical features of social networks such as high transitivity, several key network features, such as degree as well as betweenness distributions suggest fundamental differences in music collaborations and music similarity networks are created.Comment: 7 pages, 2 figure

High-sensitivity large-area photodiode read-out using a divide-and-conquer technique

In this letter, we present a novel technique to increase the sensitivity of optical read-out with large integrated photodiodes (PD). It consists of manufacturing the PD in several pieces, instead of a single device, and connecting a dedicated transimpedance amplifier (TIA) to each of these pieces. The output signals of the TIAs are combined, achieving a higher signal-to-noise ratio than with the traditional approach. This work shows a remarkable improvement in the sensitivity and transimpedance without the need for additional modifications or compensation techniques. As a result, an increase in sensitivity of 7.9 dBm and transimpedance of 8.7 dBO for the same bandwidth is achieved when dividing the photodiode read-out into 16 parallel paths. The proposed divide-and-conquer technique can be applied to any TIA design, and it is also independent of the core amplifier structure and fabrication process, which means it is compatible with every technology allowing the integration of PDs

Voltage-to-Frequency Converter for Low-Power Sensor Interfaces

This work presents a low-power rail-to-rail temperature compensated voltage-to-frequency converter (VFC) which constitutes the last stage of a sensor read-out interface targeting wireless sensor networks (WSN) applications. These quasi-digital converters are now receiving great interest, since they combine the simplicity of analog devices with the accuracy and noise immunity proper to digital signal processing; besides, frequency output is directly driven to the embedded node microcontroller C, which next performs the A/D conversion using its internal timers. A first read-out interface prototype using low-voltage low-power commercial components shows that the VFC means 99 % of the total interface consumption in read-out mode. Further, existing CMOS VFCs in the form of ASICs have a rather limited input range and an unsuitable output frequency span for typical C clock frequencies used in WSN. Hence, a novel full custom VFC solution is needed, fullfilling the main requirements of rail-to-rail operation, to take advantage of the full supply voltage range to optimize the output frequency resolution, and low-power low-voltage operation to have a power supply compatible with conventional WSN batteries while maximizing the operating life of the sensor node. Experimental results for a 0.18–μm 1.2–V CMOS VFC implementation show for an input range of (0–1.2 V) an output frequency range of (0.1–1.0 MHz), adequate to digitize the signal with the direct counting method in the sensor node μC achieving 13 bits resolution. It has a power consumption of 60 μW (35 nW in sleep mode) and it is temperature insensitive for a temperature range of (-40, 120 ºC)

Sensor-Based Seeds for a Chaotic Stream Cipher

In this paper we have used a surface micromachined capacitive accelerometer in order to generate seeds that are suitable for secure communications between wireless smart sensors for IoT networks. These seeds have then been used in a chaotic stream cipher based on a Modified Logistic Map and a Linear Feedback Shift Register. The sequences generated by the chaotic stream cipher have been subjected to the randomness NIST tests. All the tests have been passed, proving that the proposed approach could be used for secure communications

Application of a flipped classroom for model-based learning in electronics

This paper investigates the effectiveness of the flipped classroom methodology to build conceptual knowledge mentalmodels. In particular, it examines the learning process and outcomes of 40 students of a course on Physical Electronics inthe last year of a bachelor’s degree program in Physics, for which specific educational resources have been developed toimplement the flipped classroom. Among them, non-interactive resources are better to present topics and ideas, whereasinteractive resources are more useful to establish links between them to build and check the models. The examined dataentail grades, laboratory reports and rubrics, outcomes of learning activities, and direct observation, showing that theflipped classroom improves the construction of mental models, providing teaching resources where the topics and mainideas are presented, developed and exercised, and allowing students to establish links to build and check the models.Furthermore, this strategy increases the personal commitment of the students, fostering autonomy and cooperation withpeers, all of which makes it an effective pedagogical tool to build knowledge mental models

ICT-based didactic strategies to build knowledge models in electronics in higher education

This paper presents a didactic strategy based on information and communication technologies (ICTs) to help students build knowledge mental models in the context of Higher Education. It presents a methodology that combines the flipped classroom with other active methodologies and traditional lessons to improve the teaching/learning process of Electronics in university studies in Physics. Using the flipped classroom as the main strategy, the proposed methodology allows devoting more classroom time to active learning so that the instructor can follow the student learning process and evaluate model construction, while at the same time it increases student implication and fosters autonomy and cooperation with peers, contributing to a better construction of knowledge mental models in Electronics

Programmable low-power low-noise capacitance to voltage converter for MEMS accelerometers

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-µm CMOS technology and its power consumption is only 54 µW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/vHz at 50 kHz, which corresponds to 100 µg/vHz