Dynamics of polarization loss and imprint in bilayer ferroelectric tunnel junctions

This paper presents polarization loss and imprint in bilayer ferroelectric tunnel junctions as a function of relaxation time ( < 1 s) and after different SET/RESET pulses. Measurements were performed on Hf 0.5 Zr 0.5 O 2 /Al 2 O 3 stack at room temperature and systematically compared to reference samples without Al 2 O 3 . The experimental results were interpreted using self-consistent simulations coupling the polarization dynamic with charge trapping at the FE/DE interface. From this, mechanisms playing on short-term retention and imprint were explained dynamically. Amount of trapped charge modulated by amplitude and duration of SET/RESET pulses was presented as a root cause

Memory Window in Si:HfO 2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes

International audienceThe Memory Window (MW) of BEOL-integrated Si:HfO 2-based 16kbit 1T1C FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary 1T1C 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications

Crosspoint Memory Arrays: Principle, Strengths and Challenges

International audienc

Optimization of RRAM and OTS selector for advanced low voltage CMOS compatibility

International audienc

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires

National audienc

Impact of area scaling on the ferroelectric properties of back-end of line compatible Hf 0.5 Zr 0.5 O 2 and Si:HfO 2 -based MFM capacitors

International audienceScaling of planar HfO2-based ferroelectric capacitors is investigated experimentally by varying the capacitor area within 5 orders of magnitude, under the scope of limited thermal budget for crystallization. Both Hf0.5Zr0.5O2 (HZO) and Si-doped HfO2 (HSO) based metal/ferroelectric/metal (MFM) capacitors with 10 nm dielectric film thickness and TiN electrodes are demonstrated to be ferroelectric when integrated in a back-end of line (BEOL) of 130 nm CMOS technology, with a maximum thermal budget below 500°C. When the area of the ferroelectric capacitors is scaled down from 7850 µm² to 0.28 µm², no degradation of the remanent polarization (2•PR > 10 µC/cm² for HSO, > 30 µC/cm² for HZO) or of the switching kinetics (down to 100 ns at 3V) is observed. Significant improvement of the field cycling endurance is demonstrated upon area scaling, consistent with the reduction of the total number of defects when devices are shrunk. The results pave the way to future BEOL demonstrations in 130 nm and more advanced nodes with record endurance similar to perovskite ferroelectrics

Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1S1R crossbar arrays

International audienceIn this paper, we address the scalability of GeSeSbN based Ovonic Threshold Switch selector for high density crossbar integration. Impact of cell size down to 80nm on selector electrical characteristics, typical switching voltages and currents are deeply investigated on kbit arrays. Experimental results, combined with semi-analytical model, demonstrate a filamentary behavior in the OTS switching operation. OTS endurance failure is investigated. Device breakdown is correlated to a maximum amount of electronic charges flowing through the stack. Cell downscaling improves OTS insulating capabilities without any switching voltage increase, allowing high density crossbar integration and low voltage consumption, with 200Mb bank size estimated for 80nm OTS cell size with similar to 2.3V switching voltage