Molecular Beam Deposition (MBD) and Characterisation of High-k Material as Alternative Gate Oxides for MOS-Technology

Until now the forecast of the Semmiconductors Industry Association (SIA) concerning the dimension shrinking and the performance improvement of the electrical devices, reported in the International Technology Roadmap for Semiconductors (ITRS), matched very precisely the development of semiconductor process technology. But today the traditional scaling is indeed approaching the fundamental limits of the materials consituting the building blocks of the CMOS process. A big and unresolved challenge in the traditional process shrinking approach is the gate insulator. To be able to follow the dimension shrinking according to the ITRS, the SiO2 film thickness should become below 1nm within the next three years. This thickness corresponds to few atomic layers, which means that the direct tunnel leakage current through the insulator will increase. The high leakage current and the inadequate reliability for a SiO2 layer of less than 1.5nm thickness require a replacement for SiO2. To obtain high gate capacitance and inhibit tunneling, relative thick insulator of high dielectric constant (high-k) are needed to replace silicon dioxide (SiO2) as gate oxide. Therefore new materials have to be introduced into the basic CMOS structure to replace the existing ones to further extend device scaling and the reduction of the produciont costs. The present research thesis focuses on the proposition and investigation of three alternative gate oxide systems: aluminium-, praseodymium- and lanthanum oxide (Al2O3, Pr2O3 and La2O3 respectively). For each one of these systems, the growth process by Molecular Beam Deposition (MBD) has been optimised and electrical and physical characterisation has been performed to gain a better understanding of important factors associated with alternative gate dielectrics form both a theoretical and experimental point of view. Moreover, the optimisation of the interface between gate dielectric and the silicon substrate is taken into account during the development of the deposition processes. The first part of the thesis concerns the aluminium oxide. Aluminium oxide (Al2O3) is one of the first systems which have been studied to replace silicon dioxide as gate dielectric because of its large barrier height, dielectric constant twice that of SiO2, high stability and robustness. The basic properties of Al2O3 films grown on silicon substrate are well understood and for this reason alumina can be used as reference to investigate on new materials for alternative gate oxide. Beyond the aluminium oxide, lanthanide oxides have been considered as long term solution to the high-k question. In particular preseodymium oxide (Pr2O3) and lanthanum oxide (La2O3) have attracted the attention because of their high dielectric constant (20-30) and thermal stability on silicon substrate until 1000K. The properties of thin lanthanide oxide films as dielectric system for microelectronic applications are not yet completely known ind intensive research is running to find out if this dielectric will cover all the requirements needed for the new gate oxide material. In particular the major drawback of lanthanide oxide is given by its high sensibility to humidity, which leads to degradation of the dielectric film. This thesis will try to give an answer to the open questions on the investigated materials and will show the direction for future investigations

The role of the thymus in growth and development

Thesis (M.A.)--Boston University This item was digitized by the Internet Archive

A C-DAG task model for scheduling complex real-time tasks on heterogeneous platforms: preemption matters

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time application for such architectures, the designer needs to make a number of difficult choices: on which processor should a certain task be implemented? Should a component be implemented in parallel or sequentially? These choices may have a great impact on feasibility, as the difference in the processor internal architectures impact on the tasks' execution time and preemption cost. To help the designer explore the wide space of design choices and tune the scheduling parameters, in this paper we propose a novel real-time application model, called C-DAG, specifically conceived for heterogeneous platforms. A C-DAG allows to specify alternative implementations of the same component of an application for different processing engines to be selected off-line, as well as conditional branches to model if-then-else statements to be selected at run-time. We also propose a schedulability analysis for the C-DAG model and a heuristic allocation algorithm so that all deadlines are respected. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We demonstrate the effectiveness of our approach on a large set of synthetic experiments by comparing with state of the art algorithms in the literature

A Perspective on Safety and Real-Time Issues for GPU Accelerated ADAS

The current trend in designing Advanced Driving Assistance System (ADAS) is to enhance their computing power by using modern multi/many core accelerators. For many critical applications such as pedestrian detection, line following, and path planning the Graphic Processing Unit (GPU) is the most popular choice for obtaining orders of magnitude increases in performance at modest power consumption. This is made possible by exploiting the general purpose nature of today's GPUs, as such devices are known to express unprecedented performance per watt on generic embarrassingly parallel workloads (as opposed of just graphical rendering, as GPUs where only designed to sustain in previous generations). In this work, we explore novel challenges that system engineers have to face in terms of real-time constraints and functional safety when the GPU is the chosen accelerator. More specifically, we investigate how much of the adopted safety standards currently applied for traditional platforms can be translated to a GPU accelerated platform used in critical scenarios

Work-in-Progress: NVIDIA GPU Scheduling Details in Virtualized Environments

Modern automotive grade embedded platforms feature high performance Graphics Processing Units (GPUs) to support the massively parallel processing power needed for next-generation autonomous driving applications. Hence, a GPU scheduling approach with strong Real-Time guarantees is needed. While previous research efforts focused on reverse engineering the GPU ecosystem in order to understand and control GPU scheduling on NVIDIA platforms, we provide an in depth explanation of the NVIDIA standard approach to GPU application scheduling on a Drive PX platform. Then, we discuss how a privileged scheduling server can be used to enforce arbitrary scheduling policies in a virtualized environment

Building self-adaptive systems by adaptation patterns integrated into agent methodologies

Adopting patterns, i.e. reusable solutions to generic problems, turns out to be useful to rely on tested solutions and to avoid reinventing the wheel. To this aim, we proposed to use adaptation patterns to build systems that exhibit self-adaptive features. However, these patterns would be more usable if integrated in a methodology exploited to develop a system. In this paper we show how our Catalogue of adaptation patterns can be integrated into methodologies for adaptive systems; more in detail, we consider methodologies which support the development of multi-agent systems that can be considered good examples of adaptive systems. The paper, in particular, shows the integration of our Catalogue of adaptive patterns into the PASSI methodology, together with the graphical tool that we developed to support it

GPU implementation of the Frenet Path Planner for embedded autonomous systems: A case study in the F1tenth scenario

Autonomous vehicles are increasingly utilized in safety-critical and time-sensitive settings like urban environments and competitive racing. Planning maneuvers ahead is pivotal in these scenarios, where the onboard compute platform determines the vehicle's future actions. This paper introduces an optimized implementation of the Frenet Path Planner, a renowned path planning algorithm, accelerated through GPU processing. Unlike existing methods, our approach expedites the entire algorithm, encompassing path generation and collision avoidance. We gauge the execution time of our implementation, showcasing significant enhancements over the CPU baseline (up to 22x of speedup). Furthermore, we assess the influence of different precision types (double, float, half) on trajectory accuracy, probing the balance between completion speed and computational precision. Moreover, we analyzed the impact on the execution time caused by the use of Nvidia Unified Memory and by the interference caused by other processes running on the same system. We also evaluate our implementation using the F1tenth simulator and in a real race scenario. The results position our implementation as a strong candidate for the new state-of-the-art implementation for the Frenet Path Planner algorithm

Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems

Autonomous vehicles are latency-sensitive systems. The planning phase is a critical component of such systems, during which the in-vehicle compute platform is responsible for determining the future maneuvers that the vehicle will follow. In this paper, we present a GPU-accelerated optimized implementation of the Frenet Path Planner, a widely known path planning algorithm. Unlike the current state-of-the-art, our implementation accelerates the entire algorithm, including the path generation and collision avoidance phases. We measure the execution time of our implementation and demonstrate dramatic speedups compared to the CPU baseline implementation. Additionally, we evaluate the impact of different precision types (double, float, half) on trajectory errors to investigate the tradeoff between completion latencies and computation precision

API Comparison of CPU-To-GPU Command Offloading Latency on Embedded Platforms (Artifact)

High-performance heterogeneous embedded platforms allow offloading of parallel workloads to an integrated accelerator, such as General Purpose-Graphic Processing Units (GP-GPUs). A time-predictable characterization of task submission is a must in real-time applications. We provide a profiler of the time spent by the CPU for submitting stereotypical GP-GPU workload shaped as a Deep Neural Network of parameterized complexity. The submission is performed using the latest API available: NVIDIA CUDA, including its various techniques, and Vulkan. Complete automation for the test on Jetson Xavier is also provided by scripts that install software dependencies, run the experiments, and collect results in a PDF report