SABRE: A bio-inspired fault-tolerant electronic architecture

As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance. © 2013 IOP Publishing Ltd

Secondary (additional) findings from the 100,000 Genomes Project: disease manifestation, healthcare outcomes and costs of disclosure

Purpose The UK 100,000 Genomes Project offered participants screening for additional findings (AFs) in genes associated with familial hypercholesterolaemia (FH) or hereditary cancer syndromes including breast/ovarian cancer (HBOC), Lynch, familial adenomatous polyposis, MYH-associated polyposis, multiple endocrine neoplasia, von Hippel-Lindau. Here we report disclosure processes, manifestation of AF-related disease, outcomes and costs. Methods An observational study in an area representing one-fifth of England. Results Data were collected from 89 adult AF recipients. At disclosure, among 57 recipients of a cancer predisposition-associated AF and 32 recipients of an FH-associated AF, 35% and 88% respectively had personal and/or family history evidence of AF-related disease. During post-disclosure investigations, four cancer-AF recipients had evidence of disease, including one medullary thyroid cancer. Six women with an HBOC AF, three women with a Lynch syndrome AF, and two individuals with a MEN AF elected for risk-reducing surgery. New hyperlipidaemia diagnoses were made in six FH-AF recipients, and treatment (re-)initiated for seven with prior hyperlipidaemia. Generating and disclosing AFs in this region cost £1.4m; £8,680 per clinically significant AF. Conclusion Generation and disclosure of AFs identifies individuals with, and without personal or familial evidence of disease, and prompts appropriate clinical interventions. Results can inform policy towards secondary findings

Modeling Crosstalk Effects in CNT Bus Architectures

Carbon nanotubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, issues associated with crosstalk among bus lines implemented by CNTs are investigated in detail. CNT-based interconnects are modeled and the effects of crosstalk on performance and correct operation are evaluated by simulation. Existing models are modified to account for geometries in bus architectures made of parallel single-walled nanotubes and a single multiwalled nanotube. New RLC equivalent circuits are proposed for these bus architectures. A novel bus architecture with low crosstalk features is also proposed. This bus architecture is made of dual-walled nanotubes arranged in parallel. In this architecture, the crosstalk-induced delay and corresponding uncertainty (as well as crosstalk-induced peak voltage) are significantly reduced; a modest area penalty is incurred. Reductions up to 59% for the crosstalk-induced delay and up to 81% for the crosstalk-induced peak voltage are reported. These results confirm that the proposed bus arrangement noticeably improves performance and provides reliable operation

New high speed CMOS self-checking voter

Faults possibly affecting voters of TMR systems, employed in high reliability applications, can make them provide the fan-out logic with incorrect data, hence making the adoption of the TMR technique useless. In this paper we instantiate the need for self-checking voters and we propose a new self-checking voting scheme that, compared to alternate self-checking solutions, features the advantage of being faster, while requiring comparable power consumption. This is achieved at the cost of a small increase in area overhead

De l'effet destructeur d'un arrêt d'annulation sur des mesures non querellées, observations sous Conseil d'Etat, n° 19.250, 14 novembre 1978, Janssens et crts

SOMMAIRE : I. Les faits préalables à l'arrêt du 14 novembre 1978 / II. De l'effet de l'annulation d'une disposition réglementaire sur ses mesures d'application / III. Des recours querellant des mesures d'application d'une disposition réglementaire annulé

Low-Cost and Highly Reliable Detector for Transient and Crosstalk Faults Affecting FPGA Interconnects*

In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using Field Programmable Gate-Arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself, thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations

Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects

In this paper we present a novel circuit for the on-line detection of transient and crosstalk faults affecting the interconnects of systems implemented using Field Programmable Gate-Arrays (FPGAs). The proposed detector features self-checking ability with respect to faults possibly affecting itself, thus being suitable for systems with high reliability requirements, like those for space applications. Compared to alternate solutions, the proposed circuit requires a significantly lower area overhead, while implying a comparable, or lower, impact on system performance. We have verified our circuit operation and self-checking ability by means of post-layout simulations

A novel dual-walled CNT bus architecture with reduced cross-coupling features

Carbon Nano Tubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, a novel bus architecture with low crosstalk features is proposed. It is made of dual-walled nanotubes (DWNTs) arranged in parallel. It achieves reductions up to 72% of the crosstalk-induced delay, and up to 76% for the crosstalk-induced peak voltage, at a modest area increase. Therefore, the proposed bus arrangement significantly improves performance and provides reliable operation in an interconnect. © 2006 IEEE