Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a $^{28}$Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick $^{28}$Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29$\pm$0.02 $\mu$eV/sqrt(Hz) at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to cz-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a 28 Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick 28 Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz ½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to -gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system. Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28 Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise

Author Correction : Reducing charge noise in quantum dots by using thin silicon quantum wells

The original version of this Article omitted fromthe author list the author Amir Sammakwho is from the 'QuTech and Netherlands Organisation for Applied Scientific Research (TNO), Delft, The Netherlands'. This has been corrected in both the PDF and HTML versions of the Article

A singlet triplet hole spin qubit in planar Ge

Spin qubits are considered to be among the most promising candidates for building a quantum processor. GroupIV hole spin qubits have moved into the focus of interest due to the ease of operation and compatibility with Si technology. In addition, Ge offers the option for monolithic superconductor-semiconductor integration. Here we demonstrate a hole spin qubit operating at fields below 10 mT, the critical field of Al, by exploiting the large out-of-plane hole g-factors in planar Ge and by encoding the qubit into the singlet-triplet states of a double quantum dot. We observe electrically controlled g-factor-difference-driven and exchange-driven rotations with tunable frequencies exceeding 100 MHz and dephasing times of 1 $\mu$s which we extend beyond 150 $\mu$s with echo techniques. These results demonstrate that Ge hole singlet-triplet qubits are competing with state-of-the art GaAs and Si singlet-triplet qubits. In addition, their rotation frequencies and coherence are on par with Ge single spin qubits, but they can be operated at much lower fields underlining their potential for on chip integration with superconducting technologies

Low disorder and high valley splitting in silicon

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically-purified, strained quantum wells with high mobility of 3.14(8)$\times$10$^5$ cm$^2$/Vs and low percolation density of 6.9(1)$\times$10$^{10}$ cm$^{-2}$. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) $\mu$eV/Hz$^{1/2}$ and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors

Hard superconducting gap in germanium

The co-integration of spin, superconducting, and topological systems is emerging as an exciting pathway for scalable and high-fidelity quantum information technology. High-mobility planar germanium is a front-runner semiconductor for building quantum processors with spin-qubits, but progress with hybrid superconductor-semiconductor devices is hindered by the difficulty in obtaining a superconducting hard gap, that is, a gap free of subgap states. Here, we address this challenge by developing a low-disorder, oxide-free interface between high-mobility planar germanium and a germanosilicide parent superconductor. This superconducting contact is formed by the thermally-activated solid phase reaction between a metal, platinum, and the Ge/SiGe semiconductor heterostructure. Electrical characterization reveals near-unity transparency in Josephson junctions and, importantly, a hard induced superconducting gap in quantum point contacts. Furthermore, we demonstrate phase control of a Josephson junction and study transport in a gated two-dimensional superconductor-semiconductor array towards scalable architectures. These results expand the quantum technology toolbox in germanium and provide new avenues for exploring monolithic superconductor-semiconductor quantum circuits towards scalable quantum information processing.</p

Low disorder and high valley splitting in silicon

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10 cm V s and low percolation density of 6.9(1) × 10 cm. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors

Sub-nanometer mapping of strain-induced band structure variations in planar nanowire core-shell heterostructures

Strain relaxation mechanisms during epitaxial growth of core-shell nanostructures play a key role in determining their morphologies, crystal structure and properties. To unveil those mechanisms, we perform atomic-scale aberration-corrected scanning transmission electron microscopy studies on planar core-shell ZnSe@ZnTe nanowires on α-Al2O3 substrates. The core morphology affects the shell structure involving plane bending and the formation of low-angle polar boundaries. The origin of this phenomenon and its consequences on the electronic band structure are discussed. We further use monochromated valence electron energy-loss spectroscopy to obtain spatially resolved band-gap maps of the heterostructure with sub-nanometer spatial resolution. A decrease in band-gap energy at highly strained core-shell interfacial regions is found, along with a switch from direct to indirect band-gap. These findings represent an advance in the sub-nanometer-scale understanding of the interplay between structure and electronic properties associated with highly mismatched semiconductor heterostructures, especially with those related to the planar growth of heterostructured nanowire networks

Reducing charge noise in quantum dots by using thin silicon quantum wells

Charge noise degrades the performance of spin qubits hindering scalability. Here the authors engineer the heterogeneous material stack in 28Si/SiGe gate-defined quantum dots, to improve the scattering properties and to reduce charge noise