Jitter in DLL-Based Clock Multipliers caused by Delay Cell Mismatch

This paper describes the jitter problem in\ud DLL-based clock multipliers that arises due to stochastic\ud mismatch in the delay cells that are used in the Voltage Controlled\ud Delay Line of the DLL [1]. An analysis is presented\ud that relates the stochastic spread of the delay of the cells to\ud the output jitter of the clock multiplier. This analysis shows\ud that relative time deviations are highest in the middle of the\ud Delay Line and proportional to the square root of the frequency\ud multiplication factor of the structure. A circuit design\ud technique, called Impedance Level Scaling, is presented\ud that allows the designer to optimize the noise and mismatch\ud behavior of a circuit independent of other specifications such\ud as speed and linearity. Applying this technique on delay cell\ud design yields a direct trade-off between noise induced jitter\ud and power usage, and between stochastic mismatch induced\ud jitter and power usage

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply

Phase-Locked-loop with reduced clock jitter

The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop

On Jitter due to Delay Cell Mismatch in DLL-based Clock Multipliers

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the voltage controlled delay line of the DLL. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the delay line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called impedance level scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent from other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Conceptions and perceptions of urban futures in early post-war Britain: some everyday experiences of the rebuilding of Coventry, 1940-1962

Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector ( 100 ) comprising: means ( 10 ) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means ( 20 ) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q)