Implementation of the dissection theorem in cadence virtuoso

This paper describes a tool for the Cadence Virtuoso software that implements the Dissection Theorem (DT) or General Network Theorem (GNT) and its applications: the Extra Element Theorem (EET), Chain Theorem (CT) and General Feedback Theorem (GFT). The tool allows a circuit designer to gain additional circuit insight by providing all second- and third-level transfer functions of the DT. In particular, feedback networks are factored into their exact components, enabling a deeper insight into the structure of the loop gain, direct forward transmission and hence closed-loop behaviour

40-Gb/s TDM-PON downstream with low-cost EML transmitter and 3-level detection APD receiver

We report a cost-effective 40-Gb/s TDM-PON downstream utilizing an integrated DFB-EAM in OLT and an APD-based 3-level detection receiver in ONU, achieving a high power budget of 23.4 dB in real time operation

A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS

Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of >100 Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to >100 Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach >100 Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain >100 Gbaud operation with a large amount of filter taps in a compact configuration

Fast synchronization 3R burst-mode receivers for passive optical networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed

A 40 Gbaud integratedsilicon coherent receiver

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