Autoregressive time series prediction by means of fuzzy inference systems using nonparametric residual variance estimation

We propose an automatic methodology framework for short- and long-term prediction of time series by means of fuzzy inference systems. In this methodology, fuzzy techniques and statistical techniques for nonparametric residual variance estimation are combined in order to build autoregressive predictive models implemented as fuzzy inference systems. Nonparametric residual variance estimation plays a key role in driving the identification and learning procedures. Concrete criteria and procedures within the proposed methodology framework are applied to a number of time series prediction problems. The learn from examples method introduced by Wang and Mendel (W&M) is used for identification. The Levenberg–Marquardt (L–M) optimization method is then applied for tuning. The W&M method produces compact and potentially accurate inference systems when applied after a proper variable selection stage. The L–M method yields the best compromise between accuracy and interpretability of results, among a set of alternatives. Delta test based residual variance estimations are used in order to select the best subset of inputs to the fuzzy inference systems as well as the number of linguistic labels for the inputs. Experiments on a diverse set of time series prediction benchmarks are compared against least-squares support vector machines (LS-SVM), optimally pruned extreme learning machine (OP-ELM), and k-NN based autoregressors. The advantages of the proposed methodology are shown in terms of linguistic interpretability, generalization capability and computational cost. Furthermore, fuzzy models are shown to be consistently more accurate for prediction in the case of time series coming from real-world applications.Ministerio de Ciencia e Innovación TEC2008-04920Junta de Andalucía P08-TIC-03674, IAC07-I-0205:33080, IAC08-II-3347:5626

FPGA implementation of an embedded face detection system based on LEON3

This paper presents an FPGA face detection embedded system. In order achieve acceleration in the face detection process a hardware-software codesign technique is proposed. The paper describes the face detection acceleration mechanism. It also describes the implementation of an IP module that allows hardware acceleration.Comisión Europea MOBY-DIC FP7-IST-248858Ministerio de Ciencia y Tecnología TEC2011-24319Junta de Andalucía P08-TIC-0367

Design Methodology for Face Detection Acceleration

A design methodology to accelerate the face detection for embedded systems is described, starting from high level (algorithm optimization) and ending with low level (software and hardware codesign) by addressing the issues and the design decisions made at each level based on the performance measurements and system limitations. The implemented embedded face detection system consumes very little power compared with the traditional PC software implementations while maintaining the same detection accuracy. The proposed face detection acceleration methodology is suitable for real time applications.Ministerio español de Ciencia y Tecnología TEC2011-24319Junta de Andalucía FEDER P08-TIC-0367

Embedded face detection application based on local binary patterns

Comunicación presentada al "HPCC", "ICESS" y "CSS" IEEE International Conference on Embedded Software and Systems, ICESS International Symposium on Cyberspace Safety and Security, CSSIn computer vision during the recent years a new paradigm for object detection has stimulated researchers and designers interest. The foundation of this new paradigm is the Local Binary Pattern (LBP) which is a nonparametric operator that efficiently extracts the features of local structures in images. This communication describes a software embedded implementation of LBP based algorithm for object detection, in particular targeting frontal face detection

Medida y estimación activa de las prestaciones de la red

Los sistemas de medida y estimación activa de prestaciones de redes se basan en la medida de la respuesta de la red frente a tráfico de prueba transmitido entre nodos de extremo a extremo. En esta ponencia presentamos un entorno integrado de medida y estimación activa de prestaciones. El entorno generaliza, unifica y amplía el conjunto de técnicas de medida y estimación activa disponible hasta la fecha, ofreciendo una interfaz de usuario unificada, una de programación común y librerías que implementan de manera autónoma los diferentes componentes de un sistema de medida y estimación activa genérico. Se resumen asimismo las mejoras aportadas por el entorno desarrollado y su posibilidades de ampliación futura.Network performance active measurement and estimation systems are based on the response to test traffic between two end-points in the network. This paper presents an integrated environment for the active measurement and estimation of network performance. The environment has been conceived as a generalization, unification and extension to the set of active measurement and estimation techniques available to date. It offers a unified user interface, a common programming one and libraries that provide stand-alone implementations for the different components of a generic active measurement and estimation system. Contributions and improvements achieved by means of the presented environment as well as possible future extensions are also outline

Digital Implementation of SISC Fuzzy Controllers

A classification of inference systems based on approximate reasoning techniques is proposed. An alternative realization method is described for the particular SISC case, which enables reducing the silicon area and increasing the operation speed, making it especially appropriate for real time control applications

Sistema empotrado de reconocimiento de voz sobre FPGA

Comunicación presentada al "Iberchip XVIII Workshop " celebrado en Playa del Carmen (México) del 29 de Febrero al 2 de Marzo del 2012En esta comunicación se presenta un sistema empotrado sobre FPGA de reconocimiento de voz que aplica el algoritmo LPC (Linear Predictive Coding). El sistema está basado en el procesador MicroBlaze de Xilinx. Se describe el desarrollo del sistema desde la implementación del controlador del códec de audio (tanto el hardware como el desarrollo de los drivers) hasta la adaptación del algoritmo LPC a los requerimientos de la arquitectura hardware.Unión Europea MOBY-DIC Project FP7- IST-248858Ministerio de Ciencia y Tecnología (España) TEC2008-04920 TEC2011-24319Junta de Andalucía P08-TIC-03674Fondos FEDER P08-TIC-0367

Hardware/software codesign methodology for fuzzy controller implementation

This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system

Multi-input voltage and current-mode min/max circuits

This paper presents briefly a review of the different algorithms and hardware implementations for multi-input min/max operators. This allow us to show how a clever utilization of MOS devices leads to very simple current and voltage-mode min/max circuits

Open FPGA-based development platform for fuzzy systems with applications to communications

Soft computing techniques are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed communications equipment is however an open problem. This paper describes a platform for the development of fuzzy systems with applications to communications systems, namely network traffic analysis and control. An FPGA development board with PCI interface is employed to support an open platform that comprises open CAD tools as well as IP cores. For the development process, we set up a methodology and a CAD tools chain that cover from initial specification in a high-level language to implementation on FPGA devices. PCI compatible fuzzy inference modules are implemented as SoPC based on the open WISHBONE interconnection architecture. We outline results from the design and implementation of fuzzy analyzers and regulators for network traffic. These systems are shown to satisfy operational and architectural requirements of current and future high-performance routing equipment.Ministerio de Educación y Ciencia TEC2005-04359/MICJunta de Andalucía TIC2006-63