System and Method for Generating Psuedo-Noise Sequences

Disclosed is a method for generating psuedo-noise (PN) sequences utilizing a system comprised of a quantizer, and N directly quantized output/input map containing chaotic map cells, each in functional combination with combiner means and an m-bit shift register

Analog Sensing Front-End System for Harmonic Signal Classification

This paper presents the design of an Analog-to- Information spectral decomposition scheme suitable for parallel low-power analog and mixed-signal VLSI implementation. The novel scheme extracts sufficient information to achieve good back end signal detection and classification performance while using less power than purely digital spectral techniques such as FFT. Simulations of a prototype system in a mixed-signal 130nm CMOS process show a feasible solution space given an on-line self-calibrating system

A Directional Gamma Ray Detector Using a Single Chip Computational Sensor

This paper presents the design and test results of a computational radiation sensor system based on a single chip solution that can determine the direction of gamma rays emitted from a radiation source. The overall system is formed by merging a sensor section with a compact and low power computational radiation sensor section. The sensor section houses three NaI gamma ray detectors arranged in a spatial configuration that allows for direction finding. The computational sensor is based on a single chip solution developed by authors that houses multiple low power sensor front ends, event driven analog-to-digital converters, and a dedicated microcontroller on the same die. The presented system is capable of gathering the pulse height spectra from the gamma isotope data received from the three separate NaI detectors. Further processing of the data is possible by executing software algorithms using the computation resources available on chip. To that end, a compact fixed-point program was developed to perform on-chip real-time gamma ray collection and direction estimation. The single chip solution was fabricated in a 0.18 μm CMOS technology with field tests demonstrating the validity of the approaches taken. The total computational sensor system power consumption is less than 20 μW, excluding the detector power consumption. The gamma isotope direction finding program executes in less than 1 ms with 5◦ accuracy

Digital Offset Cancellation for Long Time-Constant Subthreshold OTA-C Integrators

Systems using integrators with very long time constants can place a severe constraint on allowable amplifier offset. Postfabrication cancellation of these offsets is a requirement in these applications. This brief describes the design, simulation, and measurement of a subthreshold operational transconductance amplifier (OTA) with digital calibration and its robust calibration algorithm. Statistical simulations show the scheme\u27s ability to reduce the output offset by a factor of 40. Measurements on many prototype OTAs validate the technique\u27s ability to bring the standard deviation of integrated output offset to less than 10 mV in most cases, or about 30μ V input-referred offsets. A secant-based algorithm is proposed that finds the optimum digital calibration code for each OTA in a small number of search steps that minimizes the integrated output offset. This algorithm is robust to nonmonotonic tuning characteristics, allowing the additional circuitry to be minimally sized. For low-frequency applications below 5 Hz, the scheme has nearly no net impact on die area in processes allowing circuitry below the integration capacitor

Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouri´er Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC). Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0:µm complementary metal-oxide-silicon (CMOS) integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction

A Handheld Neutron-Detection Sensor System Utilizing a New Class of Boron Carbide Diode

A handheld neutron-detection sensor application is described in this paper. The sensor system utilizes a new class of boron carbide diode that interacts with incoming neutrons. To interface with the boron carbide diode, an integrated front end is designed in a 1.5-μm standard CMOS technology. With the diode and front-end microchip, a handheld neutron-detection system was realized with an embedded microcontroller for real-time processing. The handheld detector operation was then tested with a plutonium–beryllium neutron source. Test and measurement results confirm the validity of the approach and the functionality of the design

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the desig