Venture Capital\u27s ESG Problem

Venture capital (“VC”) is repeatedly described as one of the “crown jewels” of the U.S. economy for its role in financing startups and innovation. However, recent corporate scandals, including fraud, have exposed a darker side of the VC industry and the startups in which venture capitalists (“VCs”) invest. For example, Theranos received $686 million in VC funding yet proved to be nothing more than a “house of cards” once it came to light that Theranos falsified blood test results. When Theranos founder Elizabeth Holmes was convicted of fraud, many VCs tried to distance themselves, saying Theranos was an exception and that most of Theranos’s financing did not come from VC. Nevertheless, in the wake of Theranos, fraud and mismanagement of VC-backed companies has continued

A study of jimsphere wind profiles as related to space vehicle design and operations

Winds aloft and wind shear analysis from jimsphere wind sensor balloon-radar dat

Electrical properties of Al-In-Sn alloys directionally solidified in high and low gravitational fields

The Al-In-Sn alloys were directionally solidified in the NASA KC-135 aircraft which flies a series of parabolas to generate high (high-g) and low (low-g) gravity forces parallel to the longitudinal growth axis. Thus, for a given sample, successive sections can be identified which were solidified in high-g and low-g. Measurements of the electronic properties of the samples reveal that: the resistivity of the low-g sections is larger (about a factor of 10) than that of the high-g sections; the low-g sections behave conductively like a semi-metal, while the high-g sections are essentially metallic; and both high-g and low-g sections are superconducting but the superconducting transition temperature of the low-g sections is 1 K higher than that of the high-g sections

Study of high resolution wind measuring systems. phase ii- analysis

Comparative analysis of high resolution wind measuring system

Depletion-Isolation Effect in Vertical MOSFETs During the Transition From Partial to Fully Depleted Operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

Improved drive current in RF vertical MOSFETS using hydrogen anneal

This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800 ?C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors without the hydrogen anneal. The value of drive current achieved is 250 ?A/?m, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H2 anneal is also shown to decrease the OFF-state leakage current by a factor of three

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar

110GHz fT Silicon Bipolar Transistors Implemented using Fluorine Implantation for Boron Diffusion Suppression

This paper investigates how fluorine implantation can be used to suppress boron diffusion in the base of a double polysilicon silicon bipolar transistor and hence deliver a record fT of 110 GHz. Secondary Ion Mass Spectroscopy (SIMS) and transmission electron microscopy are used to characterize the effect of the fluorine implantation energy and dose, the anneal temperature and ambient and the germanium pre-amorphisation implant on the fluorine profiles. These results show that retention of fluorine in the silicon is maximised when a high-energy fluorine implant is combined with a low thermal budget inert anneal. TEM images show that a high-energy fluorine implant into germanium pre-amorphised silicon eliminates the end of range defects from the germanium implant and produces a band of dislocation loops deeper in the silicon at the range of the fluorine implant. Boron SIMS profiles show a suppression of boron diffusion for fluorine doses at and above 5?1014cm-2, but no suppression at lower fluorine doses. This suppression of boron diffusion correlates with the appearance on the SIMS profiles of a fluorine peak at a depth of approximately Rp/2, which is attributed to fluorine trapped in vacancy-fluorine clusters. The introduction of a fluorine implant at this critical fluorine dose into a bipolar transistor process flow leads to an increase in cut-off frequency from 46 to 60GHz. Further optimisation of the base-width and the collector profile leads to a further increase in cut-off frequency to 110GHz. Two factors are postulated to contribute to the suppression of boron diffusion by the fluorine implant. First, the elimination of the germanium end of range defects, and the associated interstitial population, by the fluorine implant, removes a source of transient enhanced diffusion. Second, any interstitials released by the dislocation loops at the range of the fluorine implant would be expected to recombine at the vacancy-fluorine clusters before reaching the boron profile

Activation and functional connectivity of cerebellum during reading and during arithmetic in children with combined reading and math disabilities

Background: Reading and math constitute important academic skills, and as such, reading disability (RD or developmental dyslexia) and math disability (MD or developmental dyscalculia) can have negative consequences for children’s educational progress. Although RD and MD are different learning disabilities, they frequently co-occur. Separate theories have implicated the cerebellum and its cortical connections in RD and in MD, suggesting that children with combined reading and math disability (RD + MD) may have altered cerebellar function and disrupted functional connectivity between the cerebellum and cortex during reading and during arithmetic processing.Methods: Here we compared Control and RD + MD groups during a reading task as well as during an arithmetic task on (i) activation of the cerebellum, (ii) background functional connectivity, and (iii) task-dependent functional connectivity between the cerebellum and the cortex.Results: The two groups (Control, RD + MD) did not differ for either task (reading, arithmetic) on any of the three measures (activation, background functional connectivity, task-dependent functional connectivity).Conclusion: These results do not support theories that children’s deficits in reading and math originate in the cerebellum