Self-aligned contacts for 10nm FDSOI node : from device to circuit evaluation

We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optmimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications

Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes

session 8: advanced CMOS and New Devices ConceptsInternational audienceStacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels

3D source/drain doping optimization in multi-channel MOSFET. ESSDERC

International audienc

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration.

National audienc

(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

session New Device Architectures (G02-1168)International audienc

15nm-diameter 3D Stacked Nanowires with optional Independent Gates operation (?FET)

International audienc

Hydrogen silsesquioxane tri-dimensional advanced patterning concepts for high density of integration in sub-7 nm nodes

Best paper award; session 9: Novel Materials and TechnologiesInternational audienceRecent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps

Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications

International audienc