An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10^4 shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics

Transient currents in HfO2 and their impact on circuit and memory applications

We investigate transient currents in HfO2 dielectrics, considering their dependence on electric field, temperature and gate stack composition. We show that transient currents remain an issue even at very low temperatures and irrespective of the HfO2/SiO2 bilayer properties. Finally, we assess their impact on the reliability of precision circuit and memory applications Transient currents in HfO2 and their impact on circuit and memory applications (PDF Download Available). Available from: http://www.researchgate.net/publication/224672970_Transient_currents_in_HfO2_and_their_impact_on_circuit_and_memory_applications [accessed Oct 22, 2015]

Bipolar switching in chalcogenide phase change memory

Phase change materials based on chalcogenides are key enabling technologies for optical storage, such as rewritable CD and DVD, and recently also electrical nonvolatile memory, named phase change memory (PCM). In a PCM, the amorphous or crystalline phase affects the material band structure, hence the device resistance. Although phase transformation is extremely fast and repeatable, the amorphous phase suffers structural relaxation and crystallization at relatively low temperatures, which may affect the temperature stability of PCM state. To improve the time/temperature stability of the PCM, novel operation modes of the device should be identified. Here, we present bipolar switching operation of PCM, which is interpreted by ion migration in the solid state induced by elevated temperature and electric field similar to the bipolar switching in metal oxides. The temperature stability of the high resistance state is demonstrated and explained based on the local depletion of chemical species from the electrode region

A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS

In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time ΔΣ ADCs can’t be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of 43.4μW, corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB

A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity

A novel technique for automatic digital estimation and foreground correction of static distortion in Analog-to-Digital Converters (ADCs) is presented. The system exploits numerical Phase-Locked Loops (NPLLs) to autonomously generate a distortion-less replica of the input signal and to detect the spurs due to the ADC non linearity. The information is then fed to filters adaptively estimating, via Least Mean Squares (LMS) algorithms, a polynomial correction from the orthogonal inverse series. The solution is fully digital, does not require post-processing and can be expanded to cancel out the static distortion up to an arbitrary order. Performance is tested by simulations on a 12 bit ADC operating at 200MHz with a native Signal-to-Noise and Distortion Ratio (SINAD) of 54.9dB. Polynomial compensation up to the third order is generated in 1ms, improving the SINAD by 12dB and adding 2 effective bits of resolution and more than doubling the input range of the converter

A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors

The conventional binary weighted array successive approximation register (SAR) analog-to-digital converter (ADC) is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even if it requires extra effort to design and simulate full custom fF or sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary weighted array converters but adopting standard MiM capacitors. A monotonic switching algorithm further reduces the capacitive array consumption while an asynchronous and fully-differential dynamic logic minimizes the digital power consumption. A 10-bit prototype has been fabricated in a standard 0.13-um CMOS technology. At a 0.5-V supply and 200-kSps sampling frequency, the ADC achieves a SNDR of 52.6 dB, an ENOB of 8.45, and a power consumption of 420 nW, corresponding to a figure-of-merit (FOM) of 6 fJ/conversion-step. This efficiency is comparable to the best results published so far and it's the lowest among ADCs in 130-nm or less scaled technology. The ADC core occupies an active area of only 0.045 mm^2

A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies

The paper presents a generalization of the Groszkowski’s result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation occurs, is disclosed here for the first time. This framework is applied to Van der Pol oscillators, both nMOS and CMOS, designed in a 28-nm bulk CMOS technology. The results correctly match the oscillation frequency dependence derived from detailed circuit simulations. The analysis shows that, when even harmonics are relevant, the classical Groszkowski’s result is not able to account for close-in phase noise performance. The novel theoretical framework fully justifies, instead, the simulation results and sheds new light on the flicker noise up-conversion mechanisms in the considered oscillator structures