Theoretical and Experimental Substractions of Device Temperature Determination Utilizing I-V Characterization Applied on AlGaN/GaN HEMT

A differential analysis of electrical attributes, including the temperature profile and trapping phenomena is introduced using a device analytical spatial electrical model. The resultant current difference caused by the applied voltage variation is divided into isothermal and thermal sections, corresponding to the instantaneous time- or temperature-dependent change. The average temperature relevance is explained in the theoretical section with respect to the thermal profile and major parameters of the device at the operating point. An ambient temperature variation method has been used to determine device average temperature under quasi-static state and pulse operation, was compared with respect to the threshold voltage shift of a high-electron-mobility transistor (HEMT). The experimental sections presents theoretical subtractions of average channel temperature determination including trapping phenomena adapted for the AlGaN/GaN HEMT. The theoretical results found using the analytical model, allow for the consolidation of specific methodologies for further research to determine the device temperature based on spatially distributed and averaged parameters

Performance analysis of monolithically integrated depletion-/enhancement-mode InAlN/GaN heterostructure HEMT transistors

The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements

Charge Trap States of SiC Power TrenchMOS Transistor under Repetitive Unclamped Inductive Switching Stress

Silicon carbide (SiC) has been envisioned as an almost ideal material for power electronic devices; however, device reliability is still a great challenge. Here we investigate the reliability of commercial 1.2-kV 4H-SiC MOSFETs under repetitive unclamped inductive switching (UIS). The stress invoked degradation of the device characteristics, including the output and transfer characteristics, drain leakage current, and capacitance characteristics. Besides the shift of steady-state electrical characteristics, a significant change in switching times points out the charge trapping phenomenon. Transient capacitance spectroscopy was applied to investigate charge traps in the virgin device as well as after UIS stress. The intrinsic traps due to metal impurities or Z1,2 transitions were recognized in the virgin device. The UIS stress caused suppression of the second stage of the Z1,2  transition, and only the first stage, Z10, was observed. Hence, the UIS stress is causing the reduction of multiple charging of carbon vacancies in SiC-based devices