Un algorithme des moindres carrés parallèle à complexité réduite pour la formation de faisceaux adaptative

Ever since its inception, adaptive beamforming has become an inevitable feature in smart antenna array to improve the spectrum efficiency. However, modern embedded wireless communication systems have imposed challenging constraints on adaptive algorithms when targeting a parallel and pipelined implementation on limited resource devices, like field programmable gate array (FPGA). Such constraints include reduced complexity, parallelism, accelerated convergence and low residual error. Several variants of classical adaptive beamformers were proposed to accelerate the convergence while maintaining a low error floor. Other suggestions focused on a parallel, pipeline architecture. The resulting beamforming algorithms either presented an improved convergence profile, at the cost of an increase of complexity or presented a pipeline hardware architecture without any significant improvement. To present a unified solution with superior convergence profile while maintaining a low complexity parallel pipeline architecture, we propose a two-stages algorithm, called parallel least mean square structure (pLMS). pLMS is further simplified to obtain the reduced complexity pLMS design (RC-pLMS). In order to design a pipelined hardware architecture, we applied the delay and sum relaxation technique (DRCpLMS). A study on the behavior and the performance of different hardware design tools and processor architectures is conducted. Computer simulations demonstrated the outstanding performance of RC-pLMS. The DRC-pLMS can operate at a maximum frequency of 208.33 MHz with a minor increase in resource usage compared to LMS.Pour améliorer l’efficacité du spectre, la formation adaptative de faisceaux devient une caractéristique inévitable pour les antennes intelligentes. Les systèmes embarqués de communication sans fil imposent des contraintes difficiles liées à l’implémentation en parallèle et en pipeline avec des ressources limitées. Certaines variantes des algorithmes accélèrent la convergence tout en maintenant une faible erreur résiduelle. D’autres présentent des architectures de pipeline parallèle. Donc, les algorithmes actuels profitent d’une convergence améliorée, au prix d’une augmentation de la complexité, ou bien une architecture matérielle de pipeline sans aucune amélioration significative. Pour présenter une solution unifiée, nous proposons un algorithme en deux étapes, appelée structure parallèle des moindres carrés moyens (pLMS). Une conception de pLMS à complexité réduite (RCpLMS) a été aussi développée. Afin de concevoir une architecture matérielle en pipeline, nous avons appliqué la technique de relaxation de de somme en retard (DRCpLMS). Une étude des performances sur différents plateformes et architectures a été menée. Les simulations démontrent les performances exceptionnelles du RC-pLMS. DRCpLMS fonctionne à une fréquence maximale de 208,33 MHz avec une légère augmentation des ressources par rapport à LMS

Constant Time Hardware Architecture for a Gaussian Smoothing Filter

International audienceIn this paper a new and highly efficient hardware architecture for a bit-serial implementation of a 33 filter on FPGA is developed and presented. The concept is implemented on a Gaussian blur spatial filter and it can be extended to other filters with similar characteristics. The proposed Single Instruction Multiple Data (SIMD) architecture provides a constant operating time independent of the size of the given image while the arithmetic operations are limited to the operations of addition. The Multiple Instruction Multiple Data (MIMD) performance is achieved in a near fraction of the cost. Thus, the hardware's utilization is optimized. The total time needed to perform the filter of interest on the given image is solely dependent on the working clock frequency. The proposed design is evaluated using a small image and is implemented on two FPGA families with various sizes of an image. Also, it is compared with other architectures

GpLMS: Generalized Parallel Least Mean Square Algorithm for Partial Observations

International audienceWe propose a generalized parallel least mean square algorithm (GpLMS) to deal with partial observation scenarios. GpLMS takes advantage of a two stage parallel LMS architecture to enhance the convergence rate and updates weight vector based on observed entries to obtain a low computational complexity. We compare the results from our proposed algorithm with the state-of-the-arts in an adaptive beamforming context to illustrate its effectiveness

A Modified RC-pLMS Adaptive Beamformer for Secure Digital Communication

International audienceA modified reduced complexity parallel least mean square (mRC-pLMS) adaptive beamforming algorithm for high precision directivity and secure data communication is proposed in this paper. A high performance RC-pLMS algorithm has been proposed, recently, to eliminate the tradeoff between the LMS steady state error and its convergence speed while maintaining a low computational complexity structure. RC-pLMS is obtained by simplifying the two stages parallel LMS (pLMS) and adding a filter to the inputs, thus eliminating the need of an additional LMS filter. To further improve the RC-pLMS convergence speed and accuracy for fast and secure data communication we propose a modified RC-pLMS algorithm. mRC-pLMS is obtained by updating the RC-pLMS weight update equation to make use of the filtered input signal rather than the original input. Numerical simulations reflected by the mean square error convergence behavior and beam pattern, demonstrate the superior performance of the mRC-pLMS in providing faster convergence, lower steady state error and better interference attenuation while maintaining identical RC-pLMS resource requirements

Twiddle Factor Generation Using Chebyshev Polynomials and HDL for Frequency Domain Beamforming

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A Multi-Stage Parallel LMS Structure and its Stability Analysis Using Transfer Function Approximation

International audienceGenerally, the least mean square (LMS) adaptive algorithm is widely used in antenna array beamforming given its target tracking capability and its low computational requirements. However, the classical LMS implementation still suffers from a trade-off between convergence speed and residual error floor. Numerous variants to the classical LMS have been suggested as a solution for the previous problem at the cost of a considerable increase in the computational complexity and degraded performance in low signal to noise ratio (SNR). Thus, in this paper, we propose a multi-stage parallel LMS structure with an error feedback for accelerating the LMS convergence while maintaining a minimal steady state error and a computational complexity of order O(N), where N represents the number of antenna elements. In parallel LMS (pLMS), the second LMS stage (LMS2) error is delayed by one sample and fed-back to combine with that of the first LMS stage (LMS1) to form the total pLMS error. A transfer function approximation to the pLMS is derived in order to numerically assess the pLMS stability and to determine the approximate maximum parametric value of the step size for which the pLMS remains stable. Simulation result highlight the superior performance of the pLMS in demonstrating accelerated convergence and low steady state error compared to previous variants and for different SNR environment

Stability Analysis of the RC-PLMS Adaptive Beamformer Using a Simple Transfer Function Approximation

International audienceIn this paper, we propose a discrete time transfer function approximation for the reduced complexity parallel least mean square (RC-pLMS) adaptive beamforming algorithm. The RC-pLMS is built using a single least mean square (LMS) stage whose inputs are obtained as a linear combination of the present and past sample. Thus, in order to numerically assess the RC-pLMS stability and to determine the approximate maximum parametric value of the step size for which it remains stable, we derive its discrete time transfer function approximate. In this approximation, the input uniform linear antenna array is remodeled as a finite impulse response (FIR) fractional delay Farrow filter. Computer simulations, presented by the mean square error and beam radiation pattern, demonstrates the validity of the transfer function approximate. Additionally, the RC-pLMS stability is evaluated, with respect to the pole-zero plot, for different step sizes and the approximate upper bound value of the step size is determined

Two Stages Parallel LMS Structure: A Pipelined Hardware Architecture

International audienceModern wireless communication systems have tighten the requirements of adaptive beamformers when implemented on Field Programmable Gate Array (FPGA). The set requirements imposed additional constraints such as designing a high throughput, low complexity system with fast convergence and low steady state error. Recently, a parallel multi-stage least mean square (pLMS) structure is proposed to mitigate the listed constraints. pLMS is a two stages least mean square (LMS) operating in parallel and connected by an error feedback. To form the total pLMS error, the second LMS stage (LMS2) error is delayed by one sample and fed-back to combine with that of the first LMS stage (LMS1). pLMS provides accelerated convergence while maintaining minimal steady state error and a computational complexity of order O(N), where N represent the number of antenna elements. However, pipelining the pLMS structure is still difficult due to the LMS coefficient update loop. Thus, in this paper, we propose the application of the delay and sum relaxed look ahead technique to design a high throughput pipelined hardware architecture for the pLMS. Hence, the delayed pLMS (DpLMS) is obtained. Simulation and synthesis result, highlight the superior performance of the DpLMS in presenting a high throughput architecture while preserving accelerated convergence, low steady state error and low computational complexity. DpLMS operates at a maximum frequency of 208.33 MHz and is obtained at the cost of a marginal increase in resource requirements, i.e. additional delay registers compared to the original pLMS design

A Self Referencing Technique for the RC-pLMS Adaptive Beamformer and Its Hardware Implementation

International audienceIn this paper, we propose a self referencing scheme for the reduced complexity parallel least mean square (RC-pLMS) adaptive beamforming algorithm as means of robustness against possible interruptions in the reference signal and its hardware implementation. The RC-pLMS is a single stage, non-blind, least mean square (LMS) algorithm with modified input vectors formed as a linear combination of the current and the previous input sample. In this context, its convergence and its stability are critically dependent on the availability of its reference signal and are known to severally degrade when discontinued. Thus, for robustness against the pre-mentioned and with respect to the RC-pLMS accelerated convergence and low residual error profile, we propose the use of it’s filtered output, as an alternative learning sequence, whenever the original reference signal is discontinued, i.e. self-referencing. The proposed self referencing approach is evaluated in infinite and finite precision modes on software and on hardware, i.e. Field Programmable Gate Array (FPGA), respectively. Hardware and software simulation validates the RC-pLMS robustness against different reference signal obstruction scenarios, through the use of the proposed self-referencing approach, while maintaining an accelerated convergence behavior, a low complexity architecture and a high precision beam pointing accuracy

FFT Radix-2 and Radix-4 FPGA Acceleration Techniques Using HLS and HDL for Digital Communication Systems

International audienceFast Fourier Transform (FFT) is generally implemented on reconfigurable hardware in several signal processing or digital communication applications. It can be considered the most time and resource consuming operations due to the need of complex operations. The main of this manuscript is to investigate the contribution of High Level Synthesis (HLS) techniques on the implementation of real time FFT algorithms using field programmable gate arrays (FPGAs). In particular, this study focuses on communication systems incorporating filter-based-multicarrier modulations (FBMC), a promising candidate for the 5G technology. In order to evaluate the contribution of HLS, we implemented and tested various combinations such as: 8 and 16 points radix-2 and radix-4 FFT using finite precision, HLS tools and HDL while prompting parallelization, pipelining and hardware reuse architectures