Performance of Different Mach-Zehnder Interferometer (MZI) Structures for Optical Modulator

An optical modulator is a device that electrically controls the output phase and the output amplitude of the optical signal. This paper analyzes the performance of different structures of the MZI as an optical modulator. This project compares the performance of Y-coupler and MMI coupler as Mach-Zehnder Interferometer (MZI) modulator on the SiliconOn-Insulator (SOI). This project used OptiBPM software and OptiSys for designing the structures and performance analysis. The performance has been analyzed based on the insertion loss, extinction ratio, phase shift and modulation efficiency. MMIcoupler design shows better performance with reduced insertion loss and better modulation efficiency of 2.53% and 17% respectively than that of the Y-coupler. Furthermore, the extinction ratio and phase shift of MMI coupler show an increment about 8.35% and 7.96% respectively when analyzed as the optical modulator. Therefore, the MMI coupler as MZI modulator exhibits better performance than the Y-coupler

Overview of Positioning Techniques for LTE Technology

This paper explains about the capabilities of location positioning in wireless broadband communications and potential of hybrid positioning which are based on long term evolution (LTE) system. Mobile positioning technology has become a widely used in condition such as emergency and also in commercial services. Nowadays, with the presence of LTE technology there is a new mission on enabling Enhanced 911 (E911) and location-based services (LBS) on these 4G/5G networks. The positioning methods that were supported for LTE technology are Enhanced Cell ID (E-CID) method, Observed Time Difference of Arrival (OTDOA) and Global Navigation Satellite Systems (GNSS). A hybrid positioning system is a combination of such technologies and improves positioning accuracy by implementing the different mechanisms of the different technologies. In particular, this paper describes a concept and principle of each technique and explores important technical details of the location positioning techniques

Threshold Voltage and Leakage Current Variability on Process Parameter in a 22 nm PMOS device

This article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47% in optimising the process parameter where the implantation tilting angle is at 35°. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25% closest to the prediction value of -0.289 V ± 12.7% and minimum IOFF value which is 92% away from the predicted value which is 100 nA/µm

Optimization of Process Parameters for Threshold Voltage and Leakage Current based on Taguchi Method

In this study, the effect of process parameters on the threshold voltage (Vth) and leakage current (Ileak) were explored and the optimization of these parameters were carried out using the Taguchi method. The virtual device was initially constructed using ATHENA and ATLAS environment in Silvaco Technology Computer Aided Design (TCAD) tools. The simulation studies were directed under four varying process parameters, which are Vt adjust implantation dose, the halo tiling angle, the S/D implantation dose and the compensation implantation dose. The L9 Orthogonal Array (OA), the signalto-noise ratio (SNR), and the analysis of variance (ANOVA) were used to study the performance characteristics and to gain an optimum combination of parameter settings. It was revealed that the Vt adjust implantation dose was the most influential parameter on the Vth and Ileak. Furthermore, it also improves the device performance. The result of Vth complied with the projections made by the International Technology Roadmap for Semiconductors (ITRS)

Control Factors Optimization on Threshold Voltage and Leakage Current in 22 nm NMOS Transistor Using Taguchi Method

In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-to-Noise Ratio (SNR) analysis uses the Nominal-the-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-the-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/µm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS)

Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design

This project investigates and analyzes the impact of process parameter variance on the drive current (ION) and leakage current (IOFF) for 19nm WSi2/TiO2 NMOS device using 2k-factorial design. The four process parameter, namely halo implant dose, halo implant energy, source/drain (S/D) implant dose and S/D implant energy will be investigated and adjusted to improve the results. The simulated of the device was performed by using ATHENA module. Meanwhile the electrical characterization of the device was implemented by using ATLAS module. These two modules will be combined with 2kfactorial to aid design and optimize the process parameters. The most effective process parameter with respect ION and IOFF were chosen depending on the percentage of the factor effect on S/N ratio that indicates the relative power of factor to reduce variation. The most dominant or significant factors in S/N Ratio are pocket halo implant dose and S/D implant energy. Meanwhile, the values of ION and IOFF values for 19nm WSi2/SiO2 NMOS device after optimization approaches are 591.38 µA/µm and 2.217 pA/µm respectively. The results obtained are meet the requirement of International Technology Roadmap Semiconductor (ITRS) 2013 prediction