Electronic polarizability of superconductors and inertial mass of a moving vortex

The problem of a vortex electromagnetic mass in a superconductor is considered accounting for the self-interaction effect conditioned by the coupling of the moving vortex to the excited fluctuations of the superfluid density. The obtained polaron-type mass exceeds the earlier obtained electromagnetic mass in view of the large value of the light speed relation to the Fermi velocity and can dominate over the vortex core mass. Copyright EDP Sciences/Società Italiana di Fisica/Springer-Verlag 2005

Stress-induced effects caused by 3D IC TSV packaging in advanced semiconductor device performance

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through-silicon-via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation-based design verification flow capable to analyze a design of 3D IC stacks and to determine across-die out-of-spec variations in device electrical characteristics caused by the layout and through-silicon-via (TSV)/package-induced mechanical stress. The limited characterization/ measurement capabilities for 3D IC stacks and a strict "good die" requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design-for-manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV-based dies, stacks and packages. A set of physics-based compact models for a multi-scale simulati on to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. A strategy for generation of a simulation feeding data and respective materials characterization approach are proposed, with the goal to generate a database for multi-scale material parameters of wafer-level and package-level structures. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far