Formal connectivity verification of clock and reset signals in ultra-low-power SoC designs

Abstract. This thesis investigates the usage of formal connectivity verification on clock and reset signal connectivity in ultra-low-power SoC designs. The origin of power consumption in CMOS circuits is explained, and the conflict between dynamic and static power on system parameter level is introduced. Common power reduction techniques are introduced and explained in some detail. Overview of functional verification and its role in the design flow is presented. The main classification of functional verification into logic simulation and formal verification is discussed, and details of both are explained and compared. Challenges rising from low power design methodologies are introduced. Detailed view of connectivity and integration in SoC designs is provided, and a specified method of verifying connectivity is introduced in the form of formal connectivity verification. The practical part of the thesis starts with an explanation of the verification goal and requirements for achieving it. Structure of the design environment used in the verification task is explained, and the different stages that the verification was conducted on. Creation of used connectivity properties and the used process flow for the chosen software tool is presented. The process of confirming falsified properties as design bugs is introduced. The results of the verification task are presented, providing the total target amount for each verification stage, as well as the found bugs. The found bugs and their circumstances are explained. Comparison is made between the conventional method of verifying connectivity and the investigated formal method. Results show a great decrease in overall work effort, resourcing and time spent on the connectivity verification.Formaali liitettävyysverifiointi kello- ja reset-signaaleille ultra-matalan tehonkulutuksen järjestelmäpiireissä. Tiivistelmä. Tämä diplomityö tutkii formaalin liitettävyysverifionnin käyttöä kello- ja reset-signaalien yhteyksille ultra-matalan tehonkulutuksen järjestelmäpiireissä. Tehonkulutuksen lähteet CMOS piireissä selitetään, ja esitetään konflikti dynaamisen ja staattisen tehonkulutuksen välillä systeemin parametritasolla. Tavanomaisia tehonkulutusta vähentäviä tekniikoita esitellään ja selitetään jossain määrin. Funktionaalisen verifioinnin yleiskatsaus ja asema suunnitteluvuossa esitellään. Funktionaalisen verifioinnin pääjaottelua logiikkasimulaatioon ja formaaliin verifiointiin käsitellään, ja molempien yksityiskohtia selitetään ja vertaillaan. Matalan tehonkulutuksen metodologioiden aiheuttamat ongelmat esitetään. Yksityiskohtainen kuvaus liitettävyydestä ja integroinnista järjestelmäpiireissä selitetään, ja eritelty metodi liitettävyyden verifioimiselle esitellään formaalin liitettävyysverifionnin muodossa. Käytännön osuus diplomityöstä alkaa verifoinnin tavoitteen ja vaatimusten esittelemisellä. Käytetyn mallin rakenne ja verifiointitehtävä selitetään, sekä eri tasot joilla verifiointi suoritettiin. Liitettävyys-ominaisuuksien luominen, sekä käytetty prosessivuo valitulle työkalulle esitetään. Vääriksi todistettujen ominaisuuksien varmistaminen suunnitteluvirheiksi esitellään. Tulokset verifointitehtävästä esitellään, käsitellen verifioinnin kohteiden kokonaista lukumäärää molemmilla verifiointitasoilla, sekä niistä löydettyjen virheiden määrää. Löydetyt suunnitteluvirheet ja niiden seikkaperät selitetään. Vertailua tehdään perinteisen liitettävyyden verifionnin metodin ja tutkitun formaalin metodin välillä. Tulokset osoittavat suuren säästön kokonaisessa työmäärässä, resurssoinnissa sekä liitettävyyden verifiointiin kulutetussa ajassa

Study of heterogeneous nucleation of eutectic Si in high-purity Al-Si alloys with Sr addition

The official published version can be accessed from the link below - Copyright @ 2010 The Minerals, Metals & Materials Society and ASM InternationalAl-5 wt pct Si master-alloys with controlled Sr and/or P addition/s were produced using super purity Al 99.99 wt pct and Si 99.999 wt pct materials in an arc melter. The master-alloy was melt-spun resulting in the production of thin ribbons. The Al matrix of the ribbons contained entrained Al-Si eutectic droplets that were subsequently investigated. Differential scanning calorimetry, thermodynamic calculations, and transmission electron microscopy techniques were employed to examine the effect of the Sr and P additions on eutectic undercoolings and nucleation phenomenon. Results indicate that, unlike P, Sr does not promote nucleation. Increasing Sr additions depressed the eutectic nucleation temperature. This may be a result of the formation of a Sr phase that could consume or detrimentally affect potent AlP nucleation sites.This work is financially supported by the Higher Education Commission of Pakistan and managerially supported from the OAD

Citizen Science in Archaeology : Developing a Collaborative Web Service for Archaeological Finds in Finland

Peer reviewe

Porosity formation in aluminium alloy A356 modified with Ba, Ca, Y and Yb

An increased level of porosity is normally reported to accompany modification of Al-Si alloys. In this study, the effects of additions of barium, calcium, yttrium and ytterbium on porosity formation in an A356.0 (Al-7%Si-Mg) alloy are examined. The permanent mould casting consisted of a vertical plate connected directly to a runner at a hot-spot junction. Casting defects observed include surface shrinkage and internal porosity in the hot spot and also hot tearing of the casting and runner. All additions increased the porosity level compared to the unmodified alloy and it increased with increased addition level. The results show that additions of Ca and Y caused porosity to become increasingly concentrated in the hot spot. Additions of Ba and Yb resulted in small, round, dispersed porosity. When porosity formation is considered based on the feeding mechanisms, particularly interdendritic feeding, it is possible to rationalise the effects of the elements on porosity distribution based on their impact on the eutectic solidification mode. In Ca and Y containing alloys the eutectic evolves from the surface towards the centre of the hot spot, while heterogeneous nucleation of eutectic grains across the hot spot occurs with additions of Ba and Yb

Modification of Al-Si alloys with Ba, Ca, Y and Yb

Modification of Al-Si alloys is known to result in a depression of the eutectic arrest temperature. It has been suggested that a larger depression is related to increased modification. The effects of different concentrations of separate additions of Ba, Ca, Y and Yb on the eutectic arrest in an A356.0 (Al-7%Si-Mg) alloy have been studied by thermal analysis. All of these elements cause a depression of the eutectic arrest, however Ba and Ca result in fibrous eutectic Si while Y and Yb result in a refined plate-like eutectic silicon. Analysis of the effects of the elements on eutectic nucleation and growth temperatures and the recalescence shows two different trends. Addition of Ba and Yb both causes linear changes with increased concentration, while addition of Ca and Y result in an instantaneous effect with the first addition and no further significant changes with increased concentration