Distributed speed control for multi-three phase electrical motors with improved power sharing capability

This paper proposes a distributed speed control with improved power sharing capability for multi-three phase synchronous machines. This control technique allows the speed to be precisely regulated during power sharing transients among different drives. The proposed regulator is able to control the time constant of the current within the dq0 reference frame to a step input variation. If compared to current set-point step variations, the proposed droop controller minimises device’s stress, torque ripple, and thus mechanical vibrations. Furthermore, since distributed, it shows improved fault tolerance and reliability. The design procedure and the power sharing dynamic have been presented and analysed by means of Matlab/Simulink and validated in a 22kW experimental rig, showing good agreement with the expected performances

Adaptive saturation system for grid-tied inverters in low voltage residential micro-grids

Provision of ancillary services, like power quality improvement is a key to attain higher utilization of multifunctional grid-tied inverter. However, the power quality improvement is mainly limited by the power capacity the grid-tied inverter. This paper explores integration issues of the next-generation intermittent power sources. In particular, two different strategies for enhancing power quality given the residual power capacity of the inverters are developed. One strategy aims to obtain the expected power quality exploiting the dynamic saturation of the inverter rated apparent power and another strategy is based on peak current detection. Both strategies offer the possibility to generate appropriate references for the inner current control loop. The two proposed strategies are compared in performance, and a discussion on their practical implementation for the best performance of the inverters is provided78478915th IEEE International Conference on Environment and Electrical Engineering (EEEIC

Distributed current control for multi-three phase synchronous machines in fault conditions

Among challenges and requirements of on-going electrification process and future transportation systems there is demand for arrangements with both increased fault tolerance and reliability. Next aerospace, power-train and automotive systems exploiting new technologies are delving for new features and functionalities. Multi-three phase arrangements are one of these novel approaches where future implementation of aforementioned applications will benefit from. This paper presents and analyses distributed current control design for asymmetrical split-phase schemes composed by symmetrical three phase sections with even number of phases. The proposed design within the dq0 reference frame in nominal, open and short circuit condition of one three-phase system is compared with the vector space decomposition technique and further validated by mean of Matlab/Simulink ~R simulations

A Simple Digital Autotuning For Analog Controller in SMPS

This paper discusses the self-tuning capabilities of an analog current-mode controller for switch-mode power supplies. The proposed tuning techniques are based on the insertion of nonlinear (NL) blocks in the analog control loop and the generation of a controlled oscillation on the output voltage, in order to measure the closed-loop properties like gain margin, phase margin, and crossover frequency and to tune the analog controller according to the desired specifications. The NL blocks are based either on the NL gain or NL phase. The most relevant properties are as follows: 1) the oscillation amplitude is controlled by the NL action during the tuning procedure; 2) A/D converters are not required; 3) the parameter variations can be obtained with ancillary analog blocks (variable gain operational transconductance amplifier, switched capacitors, etc.); and 4) the tuning digital control algorithm is simple. Experimental results on a 10 A, 1.5 V point-of-load converter, where the controller tuning has been implemented using components off-the-shelf and a field-programmable gate array are provided to show the properties of the proposed syste

FPGA implementation of phase shedding with time-optimal controller in multi-phase buck converters

This paper proposes a time-optimal digital controller for the phase-shedding in multi-phase buck converters. Phase shedding is an established technique to improve the efficiency of multi-phase converters at light load, by changing the active number of phases depending on the load current level. In order to minimize the output voltage deviation due to phase shedding and the transient time required to recover the nominal operating conditions, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on the steady-state duty-cycle and the number of phases to be turned-on or turned-off. The minimum response time is achieved through a feedforward action undertaken as soon as the phase shedding command is received. The proposed approach is validated through experimental tests on a synchronous buck converter prototype. For the purpose of rapid-prototyping, the proposed digital controller is implemented in FPGA

Digital Time-Optimal Phase Shedding in Multiphase Buck Converters

This letter proposes a time-optimal digital controller for the phase shedding (PS) in multiphase buck converters. PS is an established technique to improve the efficiency of multiphase converters at light load by changing the active number of phases depending on the load-current level. In order to minimize the output-voltage deviation and the transient time during PS, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on a feedforward action, depending on the steady-state duty cycle and the number of phases to be turned on or turned off. The proposed approach is validated through experimental tests on a synchronous buck converter

A Simple Digital Auto-Tuning For Analog Controller in SMPS

This paper discusses the self-tuning capabilities of an analog current-mode controller for switch-mode DC-DC converters. The proposed tuning techniques are based on the insertion of non-linear blocks in the analog control loop and the generation of a controlled oscillation on the output voltage in order to measure the closed-loop properties like gain margin, phase margin and crossover frequency and to tune the analog controller according to the desired specifications. The non-linear blocks are based either on the non-linear gain or non-linear phase. The most relevant properties are: (1) the oscillation amplitude is controlled by the non-linear action during the tuning procedure; (2) A/D converters are not required; (3) the parameter variations can be obtained with ancillary analog blocks (variable gain operational transconductance amplifier (OTA), switched capacitors, etc.); (4) the tuning digital control algorithm is simple. Experimental results on a 10 A, 1.5 V point-of-load converter, where the controller tuning has been implemented using components off-the-shelf (COTS) and a field programmable gate array (FPGA) for the digital tuning algorithm, are provided to show the properties of the proposed system