207 research outputs found

    A versatile Montgomery multiplier architecture with characteristic three support

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    We present a novel unified core design which is extended to realize Montgomery multiplication in the fields GF(2n), GF(3m), and GF(p). Our unified design supports RSA and elliptic curve schemes, as well as the identity-based encryption which requires a pairing computation on an elliptic curve. The architecture is pipelined and is highly scalable. The unified core utilizes the redundant signed digit representation to reduce the critical path delay. While the carry-save representation used in classical unified architectures is only good for addition and multiplication operations, the redundant signed digit representation also facilitates efficient computation of comparison and subtraction operations besides addition and multiplication. Thus, there is no need for a transformation between the redundant and the non-redundant representations of field elements, which would be required in the classical unified architectures to realize the subtraction and comparison operations. We also quantify the benefits of the unified architectures in terms of area and critical path delay. We provide detailed implementation results. The metric shows that the new unified architecture provides an improvement over a hypothetical non-unified architecture of at least 24.88%, while the improvement over a classical unified architecture is at least 32.07%

    Bilateral Ota nevus in a 15 years old patient

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    Nevus of Ota is a dermal melanocytosis, clinically localizedon skin that is innervated by the first and secondbranches of the trigeminal nerve. It occurs almost entirelyin Asian people. The clinical manifestations are usuallyunilateral; only 5% of cases are bilateral. In this article,due to rarity of the case, a 15-year-old patient, who was diagnosedwith bilateral ota nevus, without having any dermatologicalcomplaints other than cosmetic appearenceand stains in her eyes and around was presented.Key words: Bilateral ota nevus, child, melanocytosi

    A rare manifestation of tuberculosis: Scrofuloderma

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    Scrofuloderma is a cutaneous manifestation of tuberculosis that results from direct extension of an underlying tuberculous focus, such as lymph node to the overlying skin. In this article, 16-year-old male patient, live in a child detention home, with a purulent, ulcerated lesion in his neck, diagnosed as Scrofuloderma was presented. The case presented in order to stress that Scrofuloderma, a rare form of tuberculosis, should be kept in mind in the differential diagnosis of chronic skin lesions

    Design and implementation of a fast and scalable NTT-based polynomial multiplier architecture

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    In this paper, we present an optimized FPGA implementation of a novel, fast and highly parallelized NTT-based polynomial multiplier architecture, which proves to be effective as an accelerator for lattice-based homomorphic cryptographic schemes. As I/O operations are as time-consuming as NTT operations during homomorphic computations in a host processor/accelerator setting, instead of achieving the fastest NTT implementation possible on the target FPGA, we focus on a balanced time performance between the NTT and I/O operations. Even with this goal, we achieved the fastest NTT implementation in literature, to the best of our knowledge. For proof of concept, we utilize our architecture in a framework for Fan-Vercauteren (FV) homomorphic encryption scheme, utilizing a hardware/software co-design approach, in which polynomial multiplication operations are offloaded to the accelerator via PCIe bus while the rest of operations in the FV scheme are executed in software running on an off-the-shelf desktop computer. Specifically, our framework is optimized to accelerate Simple Encrypted Arithmetic Library (SEAL), developed by the Cryptography Research Group at Microsoft Research, for the FV encryption scheme, where large degree polynomial multiplications are utilized extensively. The hardware part of the proposed framework targets Xilinx Virtex-7 FPGA device and the proposed framework achieves almost 11x latency speedup for the offloaded operations compared to their pure software implementations

    The Examination of Technological Device Usage and Sleep Habits among the Children Before and During the COVID-19 Pandemic

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    Objective:This study was conducted to examine the technological device usage states and sleep habits of 5-12 year-old children before and during the Coronavirus disease-2019 (COVID-19) pandemic.Materials and Methods:It is a descriptive study. This study was conducted with the parents of 488 children who were aged between 5-12 years old and studying in a kindergarten, 3 elementary schools and 3 secondary schools between March 2021 and June 2021. Data were collected by “Descriptive Information Form” and the “Children’s Sleep Habits Questionnaire (CSHQ)” in the study. Descriptive statistics and parametric tests were used to analyze the data.Results:In the study, a statistically significant difference was found in technological device usage and times of children before and during the COVID-19 pandemic period (p<0.05). It was determined that 100% of children had sleep problems clinically. A statistically significant difference was found between the mean scores of students from the CSHQ based on the education and income states of their parents (p<0.05). Additionally, a statistically significant difference was found between the mean CSHQ scores based on the duration of child’s daily technological device usage (p<0.05).Conclusion:Longer time spent with technological devices by 5-12 year old children during the COVID-19 pandemic was found to show a negative effect on the sleep habits of the children

    Accelerating LTV based homomorphic encryption in reconfigurable hardware

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    After being introduced in 2009, the first fully homomorphic encryption (FHE) scheme has created significant excitement in academia and industry. Despite rapid advances in the last 6 years, FHE schemes are still not ready for deployment due to an efficiency bottleneck. Here we introduce a custom hardware accelerator optimized for a class of reconfigurable logic to bring LTV based somewhat homomorphic encryption (SWHE) schemes one step closer to deployment in real-life applications. The accelerator we present is connected via a fast PCIe interface to a CPU platform to provide homomorphic evaluation services to any application that needs to support blinded computations. Specifically we introduce a number theoretical transform based multiplier architecture capable of efficiently handling very large polynomials. When synthesized for the Xilinx Virtex 7 family the presented architecture can compute the product of large polynomials in under 6.25 msec making it the fastest multiplier design of its kind currently available in the literature and is more than 102 times faster than a software implementation. Using this multiplier we can compute a relinearization operation in 526 msec. When used as an accelerator, for instance, to evaluate the AES block cipher, we estimate a per block homomorphic evaluation performance of 442 msec yielding performance gains of 28.5 and 17 times over similar CPU and GPU implementations, respectively

    A custom accelerator for homomorphic encryption applications

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    After the introduction of first fully homomorphic encryption scheme in 2009, numerous research work has been published aiming at making fully homomorphic encryption practical for daily use. The first fully functional scheme and a few others that have been introduced has been proven difficult to be utilized in practical applications, due to efficiency reasons. Here, we propose a custom hardware accelerator, which is optimized for a class of reconfigurable logic, for Lopez-Alt, Tromer and Vaikuntanathan’s somewhat homomorphic encryption based schemes. Our design is working as a co-processor which enables the operating system to offload the most compute–heavy operations to this specialized hardware. The core of our design is an efficient hardware implementation of a polynomial multiplier as it is the most compute–heavy operation of our target scheme. The presented architecture can compute the product of very–large polynomials in under 6.25 ms which is 102 times faster than its software implementation. In case of accelerating homomorphic applications; we estimate the per block homomorphic AES as 442 ms which is 28.5 and 17 times faster than the CPU and GPU implementations, respectively. In evaluation of Prince block cipher homomorphically, we estimate the performance as 52 ms which is 66 times faster than the CPU implementation

    Accelerating Somewhat Homomorphic Evaluation using FPGAs

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    After being introduced in 2009, the first fully homomorphic encryption (FHE) scheme has created significant excitement in academia and industry. Despite rapid advances in the last 6 years, FHE schemes are still not ready for deployment due to an efficiency bottleneck. Here we introduce a custom hardware accelerator optimized for a class of reconfigurable logic to bring LTV based somewhat homomorphic encryption (SWHE) schemes one step closer to deployment in real-life applications. The accelerator we present is connected via a fast PCIe interface to a CPU platform to provide homomorphic evaluation services to any application that needs to support blinded computations. Specifically we introduce a number theoretical transform based multiplier architecture capable of efficiently handling very large polynomials. When synthesized for the Xilinx Virtex 7 family the presented architecture can compute the product of large polynomials in under 6.256.25~msec making it the fastest multiplier design of its kind currently available in the literature and is more than 102 times faster than a software implementation. Using this multiplier we can compute a relinearization operation in 526526 msec. When used as an accelerator, for instance, to evaluate the AES block cipher, we estimate a per block homomorphic evaluation performance of 442442~msec yielding performance gains of 28.528.5 and 1717 times over similar CPU and GPU implementations, respectively

    Evaluation of Relationship Between Mandibular Third Molars and Mandibular Canal: Comparison of Findings Obtained by Panoramic Radiography and Cone-Beam Computed Tomography

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    Statement of the problem: It is important for oral surgeons to determine the precise location of mandibular third molar before extraction. The close rela-tionship of mandibular canal and mandibular third molar is a risk factor for alveolar nerve damage. Objective: The purpose of this study is to assess the relationship between mandibular canal and the mandibular third molar which has already been seen in close relationship on panoramic radiograph (PR) by the compari-son of findings of the cone-beam computed tomography (CBCT) and the PR. Materials & Methods: Close relationship between the mandibular third molar and mandibular canal was scanned in 180 patients by the PR. Images were also obtained by CBCT from patients among which a close-relationship was detected between mandibular canal and mandibular third molar. Results: Close relationship was detected between mandibular third mo-lar and mandibular canal on 26 of 180 PR and evaluated 46 mandibular third molars. In 41 cases, both the findings in PR and in CBCT images showed comp-liance with each other. As a result it was clearly seen that the mandibular third molars which were detected to be in close relationship on PR were mostly also in close relationship with mandibular canal on CBCT-images. Conclusions: If the close relationship is not seen on the panoramic ima-ges then there is no need to get CBCT for extracting the mandibular third mo-lars. By this way complication risks are eliminated with less radiation. However CBCT should be definitely used in cases which complete assessment cannot be made in no way due to artifacts such as superposition in PR

    A case of primary hypoparathyroidism presenting with acute kidney injury secondary to rhabdomyolysis

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    Hypoparathyroidism is the most common cause of symmetric calcification of the basal ganglia. Herein, a case of primary hypoparathyroidism with severe tetany, rhabdomyolysis, and acute kidney injury is presented. A 26-year-old male was admitted to the emergency clinic with leg pain and cramps, nausea, vomiting, and decreased amount of urine. He had been treated for epilepsy for the last 10 years. He was admitted to the emergency department for leg pain, cramping in the hands and legs, and agitation multiple times within the last six months. He was prescribed antidepressant and antipsychotic medications. He had a blood pressure of 150/90 mmHg, diffuse abdominal tenderness, and abdominal muscle rigidity on physical examination. Pathological laboratory findings were as follows: creatinine, 7.5 mg/dL, calcium, 3.7 mg/dL, alanine transaminase, 4349 U/L, aspartate transaminase, 5237 U/L, creatine phosphokinase, 262.000 U/L, and parathyroid hormone, 0 pg/mL.There were bilateral symmetrical calcifications in basal ganglia and the cerebellum on computerized tomography. He was diagnosed as primary hypoparathyroidism and acute kidney injury secondary to severe rhabdomyolysis. Brain calcifications, although rare, should be considered in dealing with patients with neurological symptoms, symmetrical cranial calcifications, and calcium metabolism abnormalities
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