On-chip compensation of device-mismatch effects in analog VLSI neural networks

Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of large-scale neural networks implemented in this technology. We show compact, low-power on-chip calibration techniques that compensate for device mismatch. Our techniques enable large-scale analog VLSI neural networks with learning performance on the order of 10 bits. We demonstrate our techniques on a 64-synapse linear perceptron learning with the Least-Mean-Squares (LMS) algorithm, and fabricated in a 0.35µm CMOS process.

Fault-Tolerant Dot-Product Engines

Coding schemes are presented that provide the ability to correct and detect computational errors while using dot-product engines for integer vector--matrix multiplication. Both the $L_1$-metric and the Hamming metric are considered

Mixed-mode cellular array processor realization for analyzing brain electrical activity in epilepsy

This thesis deals with the realization of hardware that is capable of computing algorithms that can be described using the theory of polynomial cellular neural/nonlinear networks (CNNs). The goal is to meet the requirements of an algorithm for predicting the onset of an epileptic seizure. The analysis associated with this application requires extensive computation of data that consists of segments of brain electrical activity. Different types of computer architectures are overviewed. Since the algorithm requires operations in which data is manipulated locally, special emphasis is put on assessing different parallel architectures. An array computer is potentially able to perform local computational tasks effectively and rapidly. Based on the requirements of the algorithm, a mixed-mode CNN is proposed. A mixed-mode CNN combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks, whereas the integrator is digital. A/D and D/A converters are used to interface between the analog blocks and the integrator. Based on the mixed-mode CNN architecture a cellular array processor is realized. In the realized array processor the processing units are coupled with programmable polynomial (linear, quadratic and cubic) first neighborhood feedback terms. A 10 mm2, 1.027 million transistor cellular array processor, with 2×72 processing units and 36 layers of memory in each is manufactured using a 0.25 μm digital CMOS process. The array processor can perform gray-scale Heun's integration of spatial convolutions with linear, quadratic and cubic activation functions for 72×72 data while keeping all I/O operations during processing local. One complete Heun's iteration round takes 166.4 μs, while the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown. Descriptions regarding improvements in the design are also explained. The results of this thesis can be used to assess the suitability of the mixed-mode approach for implementing an implantable system for predicting epileptic seizures. The results can also be used to assess the suitability of the approach for implementing other applications.reviewe

Multifrequency Eddy Current Inspection with Continuous Wave Methods

This paper describes the application of continuous wave, multifrequency eddy current methods to nondestructive inspection of materials. A generalized description of the technology is included, follow~ d by s~me ~esults o~t~ined in multifrequency examination of tubing. A major advantage of multifrequency inspection is the ability to discriminate against unwanted test parameters. The discrimination process is effected by combining the data from individual frequencies in a manner similar to simultaneous solution of multiple equations. multifrequency tests are described showing how discrimination has been achieved against parameters such as probe motion, tube support plates and magnetic surface deposits

Design Of Dna Strand Displacement Based Circuits

DNA is the basic building block of any living organism. DNA is considered a popular candidate for future biological devices and circuits for solving genetic disorders and several other medical problems. With this objective in mind, this research aims at developing novel approaches for the design of DNA based circuits. There are many recent developments in the medical field such as the development of biological nanorobots, SMART drugs, and CRISPR-Cas9 technologies. There is a strong need for circuits that can work with these technologies and devices. DNA is considered a suitable candidate for designing such circuits because of the programmability of the DNA strands, small size, lightweight, known thermodynamics, higher parallelism, and exponentially reducing the cost of synthesizing techniques. The DNA strand displacement operation is useful in developing circuits with DNA strands. The circuit can be either a digital circuit, in which the logic high and logic low states of the DNA strand concentrations are considered as the signal, or it can be an analog circuit in which the concentration of the DNA strands itself will act as the signal. We developed novel approaches in this research for the design of digital, as well as analog circuits keeping in view of the number of DNA strands required for the circuit design. Towards this goal in the digital domain, we developed spatially localized DNA majority logic gates and an inverter logic gate that can be used with the existing seesaw based logic gates. The majority logic gates proposed in this research can considerably reduce the number of strands required in the design. The introduction of the logic inverter operation can translate the dual rail circuit architecture into a monorail architecture for the seesaw based logic circuits. It can also reduce the number of unique strands required for the design into approximately half. The reduction in the number of unique strands will consequently reduce the leakage reactions, circuit complexity, and cost associated with the DNA circuits. The real world biological inputs are analog in nature. If we can use those analog signals directly in the circuits, it can considerably reduce the resources required. Even though analog circuits are highly prone to noise, they are a perfect candidate for performing computations in the resource-limited environments, such as inside the cell. In the analog domain, we are developing a novel fuzzy inference engine using analog circuits such as the minimum gate, maximum gate, and fan-out gates. All the circuits discussed in this research were designed and tested in the Visual DSD software. The biological inputs are inherently fuzzy in nature, hence a fuzzy based system can play a vital role in future decision-making circuits. We hope that our research will be the first step towards realizing these larger goals. The ultimate aim of our research is to develop novel approaches for the design of circuits which can be used with the future biological devices to tackle many medical problems such as genetic disorders

20 years of turbo coding and energy-aware design guidelines for energy-constrained wireless applications

During the last two decades, wireless communication has been revolutionized by near-capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit error ratio (BER) than their predecessors, without requiring an increased transmission energy consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, wireless local area network, and broadcast systems. Recently, however, TCs have also been considered for energy-constrained wireless communication applications, such as wireless sensor networks and the `Internet of Things.' In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities, and hence, the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the radio frequency bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder application-specific integrated circuit (ASIC) architecture designs are exemplified, and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC

In-Memory Computing by Using Nano-ionic Memristive Devices

By reaching to the CMOS scaling limitation based on the Moore’s law and due to the increasing disparity between the processing units and memory performance, the quest is continued to find a suitable alternative to replace the conventional technology. The recently discovered two terminal element, memristor, is believed to be one of the most promising candidates for future very large scale integrated systems. This thesis is comprised of two main parts, (Part I) modeling the memristor devices, and (Part II) memristive computing. The first part is presented in one chapter and the second part of the thesis contains five chapters. The basics and fundamentals regarding the memristor functionality and memristive computing are presented in the introduction chapter. A brief detail of these two main parts is as follows: Part I: Modeling- This part presents an accurate model based on the charge transport mechanisms for nanoionic memristor devices. The main current mechanism in metal/insulator/metal (MIM) structures are assessed, a physic-based model is proposed and a SPICE model is presented and tested for four different fabricated devices. An accuracy comparison is done for various models for Ag/TiO2/ITO fabricated device. Also, the functionality of the model is tested for various input signals. Part II: Memristive computing- Memristive computing is about utilizing memristor to perform computational tasks. This part of the thesis is divided into neuromorphic, analog and digital computing schemes with memristor devices. – Neuromorphic computing- Two chapters of this thesis are about biologicalinspired memristive neural networks using STDP-based learning mechanism. The memristive implementation of two well-known spiking neuron models, Hudgkin-Huxley and Morris-Lecar, are assessed and utilized in the proposed memristive network. The synaptic connections are also memristor devices in this design. Unsupervised pattern classification tasks are done to ensure the right functionality of the system. – Analog computing- Memristor has analog memory property as it can be programmed to different memristance values. A novel memristive analog adder is designed by Continuous Valued Number System (CVNS) scheme and its circuit is comprised of addition and modulo blocks. The proposed analog adder design is explained and its functionality is tested for various numbers. It is shown that the CVNS scheme is compatible with memristive design and the environment resolution can be adjusted by the memristance ratio of the memristor devices. – Digital computing- Two chapters are dedicated for digital computing. In the first one, a development over IMPLY-based logic with memristor is provided to implement a 4:2 compressor circuit. In the second chapter, A novel resistive over a novel mirrored memristive crossbar platform. Different logic gates are designed with the proposed memristive logic method and the simulations are provided with Cadence to prove the functionality of the logic. The logic implementation over a mirrored memristive crossbars is also assessed