Zero-Delay Source-Channel Coding With a Low-Resolution ADC Front End

Motivated by the practical constraints arising in emerging sensor network and Internet-of-Things (IoT) applications, the zero-delay transmission of a Gaussian measurement over a real single-input multiple-output (SIMO) additive white Gaussian noise (AWGN) channel is studied with a low-resolution analog-to-digital converter (ADC) front end. Joint optimization of the encoder and the decoder mapping is tackled under both the mean squared error (MSE) distortion and the distortion outage probability (DOP) criteria, with an average power constraint on the channel input. Optimal encoder and decoder mappings are identified for a one-bit ADC front end under both criteria. For the MSE distortion, the optimal encoder mapping is shown to be non-linear in general, while it tends to a linear encoder in the low signal-to-noise ratio (SNR) regime, and to an antipodal digital encoder in the high SNR regime. This is in contrast to the optimality of linear encoding at all SNR values in the presence of a full-precision front end. For the DOP criterion, it is shown that the optimal encoder mapping is piecewise constant and can take only two opposite values when it is non-zero. For both the MSE distortion and the DOP criteria, necessary optimality conditions are then derived for $K$ -level ADC front ends as well as front ends with multiple one-bit ADCs. These conditions are used to obtain numerically optimized solutions. Extensive numerical results are also provided in order to gain insights into the structure of the optimal encoding and decoding mappings

Zero-delay source-channel coding

In this thesis, we investigate the zero-delay transmission of source samples over three different types of communication channel models. First, we consider the zero-delay transmission of a Gaussian source sample over an additive white Gaussian noise (AWGN) channel in the presence of an additive white Gaussian (AWG) interference, which is fully known by the transmitter. We propose three parameterized linear and non-linear transmission schemes for this scenario, and compare the corresponding mean square error (MSE) performances with that of a numerically optimized encoder, obtained using the necessary optimality conditions. Next, we consider the zero-delay transmission of a Gaussian source sample over an AWGN channel with a one-bit analog-to-digital (ADC) front end. We study this problem under two different performance criteria, namely the MSE distortion and the distortion outage probability (DOP), and obtain the optimal encoder and the decoder for both criteria. As generalizations of this scenario, we consider the performance with a K-level ADC front end as well as with multiple one-bit ADC front ends. We derive necessary conditions for the optimal encoder and decoder, which are then used to obtain numerically optimized encoder and decoder mappings. Finally, we consider the transmission of a Gaussian source sample over an AWGN channel with a one-bit ADC front end in the presence of correlated side information at the receiver. Again, we derive the necessary optimality conditions, and using these conditions obtain numerically optimized encoder and decoder mappings. We also consider the scenario in which the side information is available also at the encoder, and obtain the optimal encoder and decoder mappings. The performance of the latter scenario serves as a lower bound on the performance of the case in which the side information is available only at the decoder.Open Acces

Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission

This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation

Analog Cancellation of a Known Remote Interference: Hardware Realization and Analysis

The onset of quantum computing threatens commonly used schemes for information secrecy across wireless communication channels, particularly key-based data-level encryption. This calls for secrecy schemes that can provide everlasting secrecy resistant to increased computational power of an adversary. One novel physical layer scheme proposes that an intended receiver capable of performing analog cancellation of a known key-based interference would hold a significant advantage in recovering small underlying messages versus an eavesdropper performing cancellation after analog-to-digital conversion. This advantage holds even in the event that an eavesdropper can recover and use the original key in their digital cancellation. Inspired by this scheme, a flexible software-defined radio receiver design capable of maintaining analog cancellation ratios consistently over 40 dB, reaching up to and over 50 dB, is implemented in this thesis. Maintaining this analog cancellation requires very precise time-frequency synchronization along with accurate modeling and simulation of the channel effects on the interference. The key sources of synchronization error preventing this test bed from achieving and maintaining perfect interference cancellation, sub-sample period timing errors and limited radio frequency stability, are explored for possible improvements. To further prove robustness of the implemented secrecy scheme, the testbed is shown to operate with both phase-shift keying and frequency-modulated waveforms. Differences in the synchronization algorithm used for the two waveforms are highlighted. Interference cancellation performance is measured for increasing interference bandwidth and shown to decrease with such. The implications this testbed has on security approaches based on intentional interference employed to confuse eavesdroppers is approached from the framework proposed in the motivating everlasting secrecy scheme. Using analog cancellation levels from the hardware testbed, it is calculated that secrecy rates up to 2.3 bits/symbol are gained by receivers (intended or not) performing interference cancellation in analog rather than on a digital signal processor. Inspired by the positive gains in secrecy over systems not performing analog cancellation prior to signal reception, a novel secrecy scheme that focuses on the advantage an analog canceller holds in receiver amplifier compression is proposed here. The adversary amplifier is assumed to perform linear cancellation after the interference has passed through their nonlinear amplifier. This is accomplished by deriving the distribution of the interference residual after undergoing an inverse tangent transfer function and perfect linear cancellation. Parameters of this scheme are fit for the radios and cancellation ratios observed in the testbed, resulting in a secrecy gain of 0.95 bits/symbol. The model shows that larger message powers can still be kept secure for the achieved levels of cancellation, thus providing an even greater secrecy gain with increased message transmission power

Ultra-Wideband Secure Communications and Direct RF Sampling Transceivers

Larger wireless device bandwidth results in new capabilities in terms of higher data rates and security. The 5G evolution is focus on exploiting larger bandwidths for higher though-puts. Interference and co-existence issues can also be addressed by the larger bandwidth in the 5G and 6G evolution. This dissertation introduces of a novel Ultra-wideband (UWB) Code Division Multiple Access (CDMA) technique to exploit the largest bandwidth available in the upcoming wireless connectivity scenarios. The dissertation addresses interference immunity, secure communication at the physical layer and longer distance communication due to increased receiver sensitivity. The dissertation presents the design, workflow, simulations, hardware prototypes and experimental measurements to demonstrate the benefits of wideband Code-Division-Multiple-Access. Specifically, a description of each of the hardware and software stages is presented along with simulations of different scenarios using a test-bench and open-field measurements. The measurements provided experimental validation carried out to demonstrate the interference mitigation capabilities. In addition, Direct RF sampling techniques are employed to handle the larger bandwidth and avoid analog components. Additionally, a transmit and receive chain is designed and implemented at 28 GHz to provide a proof-of-concept for future 5G applications. The proposed wideband transceiver is also used to demonstrate higher accuracy direction finding, as much as 10 times improvement

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested