Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Issues concerning centralized versus decentralized power deployment

The results of a study of proposed lunar base architectures to identify issues concerning centralized and decentralized power system deployment options are presented. The power system consists of the energy producing system (power plant), the power conditioning components used to convert the generated power into the form desired for transmission, the transmission lines that conduct this power from the power sources to the loads, and the primary power conditioning hardware located at the user end. Three power system architectures, centralized, hybrid, and decentralized, were evaluated during the course of this study. Candidate power sources were characterized with respect to mass and radiator area. Two electrical models were created for each architecture to identify the preferred method of power transmission, dc or ac. Each model allowed the transmission voltage level to be varied at assess the impact on power system mass. The ac power system models also permitted the transmission line configurations and placements to determine the best conductor construction and installation location. Key parameters used to evaluate each configuration were power source and power conditioning component efficiencies, masses, and radiator areas; transmission line masses and operating temperatures; and total system mass

Inherently workload-balanced clustered microarchitecture

The performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, reducing communication penalties and balancing the workload are opposite targets, since improving one usually implies a detriment in the other. In this paper we propose a new clustered microarchitecture that can minimize communication penalties without compromising workload balance. The key idea is to arrange the clusters in a ring topology in such a way that results of one cluster can be forwarded to the neighbor cluster with a very short latency. In this way, minimizing communication penalties is favored when the producer of a value and its consumer are placed in adjacent clusters, which also favors workload balance. The proposed microarchitecture is shown to outperform a state-of-the-art clustered processor. For instance, for an 8-cluster configuration and just one fully pipelined unidirectional bus, 15% speedup is achieved on average for FP programs.Peer ReviewedPostprint (published version

A GA-based simulation system for WMNs: comparison analysis for different number of flows, client distributions, DCF and EDCA functions

In this paper, we compare the performance of Distributed Coordination Function (DCF) and Enhanced Distributed Channel Access (EDCA) for normal and uniform distributions of mesh clients considering two Wireless Mesh Network (WMN) architectures. As evaluation metrics, we consider throughput, delay, jitter and fairness index metrics. For simulations, we used WMN-GA simulation system, ns-3 and Optimized Link State Routing. The simulation results show that for normal distribution, the throughput of I/B WMN is higher than Hybrid WMN architecture. For uniform distribution, in case of I/B WMN, the throughput of EDCA is a little bit higher than Hybrid WMN. However, for Hybrid WMN, the throughput of DCF is higher than EDCA. For normal distribution, the delay and jitter of Hybrid WMN are lower compared with I/B WMN. For uniform distribution, the delay and jitter of both architectures are almost the same. However, in the case of DCF for 20 flows, the delay and jitter of I/B WMN are lower compared with Hybrid WMN. For I/B architecture, in case of normal distribution the fairness index of DCF is higher than EDCA. However, for Hybrid WMN, the fairness index of EDCA is higher than DCF. For uniform distribution, the fairness index of few flows is higher than others for both WMN architectures.Peer ReviewedPostprint (author's final draft

Array-based architecture for FET-based, nanoscale electronics

Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading