Facile fabrication of stretchable Ag nanowire/polyurethane electrodes using high intensity pulsed light

Silver nanowires (AgNWs) have emerged as a promising nanomaterial for next generation stretchable electronics. However, until now, the fabrication of AgNW-based components has been hampered by complex and time-consuming steps. Here, we introduce a facile, fast, and one-step methodology for the fabrication of highly conductive and stretchable AgNW/polyurethane (PU) composite electrodes based on a high-intensity pulsed light (HIPL) technique. HIPL simultaneously improved wire-wire junction conductivity and wire-substrate adhesion at room temperature and in air within 50 mu s, omitting the complex transfer-curing-implanting process. Owing to the localized deformation of PU at interfaces with AgNWs, embedding of the nanowires was rapidly carried out without substantial substrate damage. The resulting electrode retained a low sheet resistance (high electrical conductivity) of <10 Omega/sq even under 100% strain, or after 1,000 continuous stretching-relaxation cycles, with a peak strain of 60%. The fabricated electrode has found immediate application as a sensor for motion detection. Furthermore, based on our electrode, a light emitting diode (LED) driven by integrated stretchable AgNW conductors has been fabricated. In conclusion, our present fabrication approach is fast, simple, scalable, and cost-efficient, making it a good candidate for a future roll-to-roll process

Application of nanomaterials in two-terminal resistive-switching memory devices

Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs), nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well

Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 x 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10^11 b/cm^2

Washington University Record, February 3, 2000

https://digitalcommons.wustl.edu/record/1851/thumbnail.jp

AN OVERVIEW OF NANOELECTRONICS AND NANODEVICES

Nanoelectronics is a nascent area of making electronic devices at the atomic scale to utilize small-scale 'quantum' characteristics of nature. As the name suggests, Nanoelectronics refers to employing nanotechnology in building electronic devices/components; especially transistors. Thus, transistor devices which are so small such that inter-atomic cooperation and quantum mechanical characteristics cannot be ignored are known as Nanoelectronics. This article presents Nanoelectronics and Nanodevices, which are the critical enablers that will not only enable mankind to exploit the ultimate technological capabilities of electronic, mechanical, magnetic, and biological systems but also have the potential to play a part in transforming of the systems thus giving rise to new trends that will revolutionize our life style

AN OVERVIEW OF NANOELECTRONICS AND NANODEVICES

Nanoelectronics is a nascent area of making electronic devices at the atomic scale to utilize small-scale 'quantum' characteristics of nature. As the name suggests, Nanoelectronics refers to employing nanotechnology in building electronic devices/components; especially transistors. Thus, transistor devices which are so small such that inter-atomic cooperation and quantum mechanical characteristics cannot be ignored are known as Nanoelectronics. This article presents Nanoelectronics and Nanodevices, which are the critical enablers that will not only enable mankind to exploit the ultimate technological capabilities of electronic, mechanical, magnetic, and biological systems but also have the potential to play a part in transforming of the systems thus giving rise to new trends that will revolutionize our life style

Magnetotaxis as a Means for Nanofabrication

Magnetotactic bacteria (MTB), discovered in early 1970s contain single-domain crystals of magnetite (Fe3O4) called magnetosomes that tend to form a chain like structure from the proximal to the distal pole along the long axis of the cell. The ability of these bacteria to sense the magnetic field for displacement, also called magnetotaxis, arises from the magnetic dipole moment of this chain of magnetosomes. In aquatic habitats, these organisms sense the geomagnetic field and traverse the oxic-anoxic interface for optimal oxygen concentration along the field lines. Here we report an elegant use of MTB where magnetotaxis of Magnetospirillum magneticum (classified as AMB-1) could be utilized for controlled navigation over a semiconductor substrate for selective deposition. We examined 50mm long coils made out of 18AWG and 20AWG copper conductors having diameters of 5mm, 10mm and 20mm for magnetic field intensity and heat generation. Based on the COMSOL simulations and experimental data, it is recognized that a compound semiconductor manufacturing technology involving bacterial carriers and carbon-based materials such as graphene and carbon nanotubes would be a desirable choice in the future

Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio