17,259 research outputs found
Architectures for RF Frequency synthesizers
Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud
Written for:\ud
Electrical and electronic engineer
Cycle Accurate Energy and Throughput Estimation for Data Cache
Resource optimization in energy constrained real-time adaptive embedded systems highly depends on accurate energy and throughput estimates of processor peripherals. Such applications require lightweight, accurate mathematical models to profile energy and timing requirements on the go. This paper presents enhanced mathematical models for data cache energy and throughput estimation. The energy and throughput models were found to be within 95% accuracy of per instruction energy model of a processor, and a full system simulator?s timing model respectively. Furthermore, the possible application of these models in various scenarios is discussed in this paper
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Neuromorphic computing systems comprise networks of neurons that use
asynchronous events for both computation and communication. This type of
representation offers several advantages in terms of bandwidth and power
consumption in neuromorphic electronic systems. However, managing the traffic
of asynchronous events in large scale systems is a daunting task, both in terms
of circuit complexity and memory requirements. Here we present a novel routing
methodology that employs both hierarchical and mesh routing strategies and
combines heterogeneous memory structures for minimizing both memory
requirements and latency, while maximizing programming flexibility to support a
wide range of event-based neural network architectures, through parameter
configuration. We validated the proposed scheme in a prototype multi-core
neuromorphic processor chip that employs hybrid analog/digital circuits for
emulating synapse and neuron dynamics together with asynchronous digital
circuits for managing the address-event traffic. We present a theoretical
analysis of the proposed connectivity scheme, describe the methods and circuits
used to implement such scheme, and characterize the prototype chip. Finally, we
demonstrate the use of the neuromorphic processor with a convolutional neural
network for the real-time classification of visual symbols being flashed to a
dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure
On Path Memory in List Successive Cancellation Decoder of Polar Codes
Polar code is a breakthrough in coding theory. Using list successive
cancellation decoding with large list size L, polar codes can achieve excellent
error correction performance. The L partial decoded vectors are stored in the
path memory and updated according to the results of list management. In the
state-of-the-art designs, the memories are implemented with registers and a
large crossbar is used for copying the partial decoded vectors from one block
of memory to another during the update. The architectures are quite area-costly
when the code length and list size are large. To solve this problem, we propose
two optimization schemes for the path memory in this work. First, a folded path
memory architecture is presented to reduce the area cost. Second, we show a
scheme that the path memory can be totally removed from the architecture.
Experimental results show that these schemes effectively reduce the area of
path memory.Comment: 5 pages, 6 figures, 2 table
Opportunities for aircraft controls research
Several problems which drive aircraft control technology are discussed. Highly unstable vehicles, flutter speed boundary expansion, and low level automated flight that follows terrain are discussed
Instruction fetch architectures and code layout optimizations
The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing a higher performance processor implies balancing all the pipeline stages to ensure that overall performance is not dominated by any of them. This means that a faster execution engine also requires a faster fetch engine, to ensure that it is possible to read and decode enough instructions to keep the pipeline full and the functional units busy. This paper explores the challenges faced by the instruction fetch stage for a variety of processor designs, from early pipelined processors, to the more aggressive wide issue superscalars. We describe the different fetch engines proposed in the literature, the performance issues involved, and some of the proposed improvements. We also show how compiler techniques that optimize the layout of the code in memory can be used to improve the fetch performance of the different engines described Overall, we show how instruction fetch has evolved from fetching one instruction every few cycles, to fetching one instruction per cycle, to fetching a full basic block per cycle, to several basic blocks per cycle: the evolution of the mechanism surrounding the instruction cache, and the different compiler optimizations used to better employ these mechanisms.Peer ReviewedPostprint (published version
Improving Fixed-Point Implementation of QR Decomposition by Rounding-to-Nearest
QR decomposition is a key operation in many
current communication systems. This paper shows how to reduce
the area of a fixed-point QR decomposition implementation
based on Givens rotations by using a new number representation
system. This new representation allows performing round-tonearest
at the same cost of truncation. Consequently, the
rounding errors of the results are halved, which allows it to
reduce the word-length by one bit. This reduction positively
impacts on the area, delay and power consumption of the design.Ministry of Education and Science of Spain and Junta of AndalucĂa under contracts TIN2013-42253-P
and TIC-1692, respectively, and Universidad de Málaga. Campus de Excelencia Internacional AndalucĂa Tech
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