Wafer bonding and layer transfer processes for 4-junction high efficiency solar cells

A four-junction cell design consisting of InGaAs, InGeAsP, GaAs, and Ga0.5In0.5P subcells could reach 1 x AMO efficiencies of 35.4%. but relies on the integration of non-lattice-matched materials. Wafer bonding and layer transfer processes show promise in the fabrication of InP/Si epitaxial templates for growth of the bottom InGaAs and InGaAsP subcells on a Si support substrate. Subsequent wafer bonding and layer transfer of a thin Ge layer onto the lower subcell stack can serve as an epitaxial template for GaAs and Ga0.5In0.5P subcelis. Present results indicate that optically active III/V compound semiconductors can be grown on both Ge/Si and InP/Si heterostructures. Current-voltage electrical characterization of the interfaces of these structures indicates that both InP/Si and Ge/Si interfaces have specific resistances lower than 0.1 Ωcm^2 for heavily doped wafer bonded interfaces, enabling back surface power extraction from the finished cell structure

Wafer bonding solution to epitaxial graphene - silicon integration

The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.Comment: 15 pages, 7 figure

Nanomechanical optical devices fabricated with aligned wafer bonding

This paper reports on a new method for making some types of integrated optical nanomechanical devices. Intensity modulators as well as phase modulators were fabricated using several silicon micromachining techniques, including chemical mechanical polishing and aligned wafer bonding. This new method enables batch fabrication of the nanomechanical optical devices, and enhances their performance

Wafer bonding technologies for nano-, micro- and macro-system realization and integration

This paper is providing an overview about most common wafer bonding technologies used for the realization of nano-, micro,- and macro systems and for system integration. At first, the general aspects of wafer bonding applications are discussed. This is followed by the technological description of different wafer bonding processes, since for different bonding applications different processes are required related to process integration and the actual surface layers on the wafers which should be bonded. Finally, benefits and drawbacks as well as technology and application aspects are shown in an overview table, providing systematization and detailed comparison of the described bonding processes. This overview should help to choose the best suitable process for wafer level bonding and other applications

Fabrication of capacitive micromachined ultrasonic transducers for underwater applications using thermocompression wafer-bonder

Capacitive Micromachined Ultrasonic Transducers (CMUTs) are the prospective alternative to the traditional piezoelectric ultrasonic transducers. CMUTs are essentially parallel plate capacitors produced using Microelectromechanical Systems (MEMS) technology. The production of CMUTs is broken down into sacrificial underetching and wafer bonding methods. The sacrificial release-based techniques are complex and require several adjustments in terms of optimizing fabrication steps and material selections. Further, the sacrificial release-based processes need ultimate control over the gap height and membrane thickness. On the contrary, the wafer bonding fabrication processes are not only simpler than the sacrificial release methods but also provide a very good parametric control over the membrane thickness and gap height. Besides its advantages, the wafer bonding methods are very sensitive to contamination and surface roughness. The surface roughness problems are addressed by either using the costly Silicon-on-Insulator (SOI) wafers or by using complex Chemical Mechanical Polishing (CMP) method. This article presents a simple and economical CMUTs wafer bonding fabrication method. A thermocompression based metal bonded technique is adopted to successfully fabricate low frequency CMUTs to be used for underwater applications

Ultrathin silicon wafer bonding physics and applications

Ultrathin silicon wafer bonding is an emerging process that simplifies device fabrication, reduces manufacturing costs, increases yield, and allows the realization of novel devices. Ultrathin silicon wafers are between 3 and 200 microns thick with all the same properties of the thicker silicon wafers (greater than 300 microns) normally used by the semiconductor electronics industry. Wafer bonding is one technique by which multiple layers are formed. In this thesis, the history and practice of wafer bonding is described and applied to the manufacture of microelectomechanical systems (MEMS) devices with layer thickness on the scale of microns. Handling and processing problems specific to ultrathin silicon wafers and their bonding are addressed and solved. A model that predicts the conformal nature of these flexible silicon wafers and its impact on bonding is developed in terms of a relatively new description of surface quality, the Power Spectral Density (PSD). A process for reducing surface roughness of silicon is elucidated and a model of this process is described. A method of detecting particle contamination in chemical baths and other processes using wafer bonding is detailed. A final section highlights some recent work that has used ultrathin silicon wafer bonding to fabricate MEMS devices that have reduced existing design complexity and made possible novel, and otherwise difficult to produce, sensors. A new fabrication process that can reduce the required time for proof-of-principle devices using ultrathin silicon wafers is also described

Gold Thermocompression Wafer Bonding

Thermocompression bonding of gold is a promising technique for the fabrication and packaging microelectronic and MEMS devices. The use of a gold interlayer and moderate temperatures and pressures results in a hermetic, electrically conductive bond. This paper documents work conducted to model the effect of patterning in causing pressure non-uniformities across the wafer and its effect on the subsequent fracture response. A finite element model was created that revealed pattern-dependent local pressure variations of more than a factor of three. This variation is consistent with experimental observations of bond quality across individual wafers A cohesive zone model was used to investigate the resulting effect of non-uniform bond quality on the fracture behavior. A good, qualitative agreement was obtained with experimental observations of the load-displacement response of bonds in fracture tests.Singapore-MIT Alliance (SMA

SOI via Wafer Bonding

An attempt is made at the preparation of silicon-on-insulator (SOl) substrates suitable for device fabrication. This is done by the high temperature bonding of a pair of silicon wafers upon which oxide layers have been thermally grown. One of the pair is then ground back to a suitable thickness. Bonding strength and defects are also evaluated

Low temperature sacrificial wafer bonding for planarization after very deep etching

A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of (1) polymer bonding followed by dry etching and (2) anodic bonding combined with KOH etching are discussed. The polymer bond method was applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridge