Implementation of an Improved Image Enhancement Algorithm on FPGA

Image processing plays very crucial role in this digital human world and has rapidly evolved with the development of computers, mathematics and the real-life demand of variety of applications in wide range of areas. This wide range of areas includes remote sensing, machine/ robot vision, pattern recognition, medical diagnosis, video processing, military, agriculture, television, etc. Image processing has two important components which are image enhancement and information extraction. Since image enhancement works at the front end with the initial raw inputs, it works like a backbone in image processing. When it comes to implementing these image enhancement techniques and developing applications, these tasks are bit demanding in the choice of processing units because the demand of high resolution. This emerges the necessity of a high speed, powerful and cost-effective processing unit. In this thesis we present an improved image enhancement algorithm in terms of performance and its implementation on FPGA as they satiates the necessity of high speed, powerful and cost-effective processing unit by providing flexibility, parallelization, pipelining and reconfigurability. We have performed a high level synthesis by using MATLAB and implemented an improved image enhancement algorithm on Cyclone V by using Quartus Prime. We have considered an X-ray image size of 1000x1920p for implementation and achieved decent PSNR values and hardware resource utilization along with the better visual interpretability by our proposed improvements. For achieving a better execution time and power consumption we also offer the task parallelism for the algorithm

Implementation Of An Improved Image Enhancement Algorithm On FPGA

Image processing plays very crucial role in this digital human world and has rapidly evolved with the development of computers, mathematics and the real-life demand of variety of applications in wide range of areas. This wide range of areas includes remote sensing, machine/ robot vision, pattern recognition, medical diagnosis, video processing, military, agriculture, television, etc. Image processing has two important components which are image enhancement and information extraction. Since image enhancement works at the front end with the initial raw inputs, it works like a backbone in image processing. When it comes to implementing these image enhancement techniques and developing applications, these tasks are bit demanding in the choice of processing units because the demand of high resolution. This emerges the necessity of a high speed, powerful and cost-effective processing unit. In this thesis we present an improved image enhancement algorithm in terms of performance and its implementation on FPGA as they satiates the necessity of high speed, powerful and cost-effective processing unit by providing flexibility, parallelization, pipelining and reconfigurability. We have performed a high level synthesis by using MATLAB and implemented an improved image enhancement algorithm on Cyclone V by using Quartus Prime. We have considered an X-ray image size of 1000x1920p for implementation and achieved decent PSNR values and hardware resource utilization along with the better visual interpretability by our proposed improvements. For achieving a better execution time and power consumption we also offer the task parallelism for the algorithm

ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications

Future computing systems will require dedicated accelerators to achieve high-performance. The mini-symposium ParaFPGA explores parallel computing with FPGAs as an interesting avenue to reduce the gap between the architecture and the application. Topics discussed are the power of functional and dataflow languages, the performance of high-level synthesis tools, the automatic creation of hardware multi-cores using C-slow retiming, dynamic power management to control the energy consumption, real-time reconfiguration of streaming image processing filters and memory optimized event image segmentation

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications. The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The CGRAs are ASICs and therefore, expensive to produce. However, Field Programmable Gate Arrays (FPGAs) are relatively cheaper for low volume products but they are not so easily programmable. We combine best of both worlds by implementing a Virtual Coarse-Grained Reconfigurable Array (VCGRA) on FPGA. VCGRAs are a trade off between FPGA with large routing overheads and ASICs. In this perspective we present a novel heterogeneous Virtual Coarse-Grained Reconfigurable Array (VCGRA) called "Pixie" which is suitable for implementing high performance image processing applications. The proposed VCGRA contains generic processing elements and virtual channels that are described using the Hardware Description Language VHDL. Both elements have been optimized by using the parameterized configuration tool flow and result in a resource reduction of 24% for each processing elements and 82% for each virtual channels respectively.Comment: Presented at 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017) arXiv:1704.0880

Towards a Scalable Hardware/Software Co-Design Platform for Real-time Pedestrian Tracking Based on a ZYNQ-7000 Device

Currently, most designers face a daunting task to research different design flows and learn the intricacies of specific software from various manufacturers in hardware/software co-design. An urgent need of creating a scalable hardware/software co-design platform has become a key strategic element for developing hardware/software integrated systems. In this paper, we propose a new design flow for building a scalable co-design platform on FPGA-based system-on-chip. We employ an integrated approach to implement a histogram oriented gradients (HOG) and a support vector machine (SVM) classification on a programmable device for pedestrian tracking. Not only was hardware resource analysis reported, but the precision and success rates of pedestrian tracking on nine open access image data sets are also analysed. Finally, our proposed design flow can be used for any real-time image processingrelated products on programmable ZYNQ-based embedded systems, which benefits from a reduced design time and provide a scalable solution for embedded image processing products