Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software

A deep-learning inference accelerator is synthesized from a C-language software program parallelized with Pthreads. The software implementation uses the well-known producer/consumer model with parallel threads interconnected by FIFO queues. The LegUp high-level synthesis (HLS) tool synthesizes threads into parallel FPGA hardware, translating software parallelism into spatial parallelism. A complete system is generated where convolution, pooling and padding are realized in the synthesized accelerator, with remaining tasks executing on an embedded ARM processor. The accelerator incorporates reduced precision, and a novel approach for zero-weight-skipping in convolution. On a mid-sized Intel Arria 10 SoC FPGA, peak performance on VGG-16 is 138 effective GOPS

6502 emulator on FPGA

6502 microprocessor was once used in almost all of the microcomputer in the 80s, including the Apple II lines of computer, the Commodore PET, the Commodore 64, the Atari 8-bit series and even on the Nintendo Entertainment System (NES) video game console. The objective of this project is to emulate the once famous 6502 microprocessor onto a FPGA chip. The FPGA-based 6502 microprocessor had to emulate the functionality of a real 6502 microprocessor. Accurate pinouts emulation is desired but not a must. The 6502 assembly language is easy to learn and building a computer based on this microprocessor requires very few parts, thus making this project a great experiential learning process. The scope of this project requires the student to have an in-depth understanding on computer system architecture, especially on 6502 architecture; V erilog to understand existing 6502 source code from Bird Computer and also FPGA development process (synthesis tools) to transfer the Verilog code to the FPGA chip. Thus far, the resources and information on 6502 microprocessor looks promising. The student earlier scope was to come up with the 6502 code in Verilog HDL, but as there is available code from Bird Computer (State Machine coded) so the student had chanced his objectives to understand the existing code and implement it on FPGA only. But as along the way, problems occur on hardware implementation, focus had been switched again to simulate the existing code or ALU or simple processor to build up student understanding and for documentation for future project expansion. To test the functionality of the 6502 system, the student will either find existing application or come up with simple program to run using the FPGA-based 6502 system

A Comparative Study of Chisel for FPGA Design

This paper presents the results of a comparative study conducted into designing with the Chisel hardware construction language against the Verilog hardware description language across a range of standard-library and bespoke FPGA design components including an N-bit FIFO, a round-robin arbiter and a complex, scalable arbiter. Comparison metrics such as maximum operating frequency, silicon area, design flow run-time, source-code density and maintainability, simulation run-time and speed of coding are employed to evaluate the merits of designing with Chisel. Each component is implemented with a deep low-level hardware understanding with an aim to evaluate the merits of designing with Chisel from a hardware designers\u27 perspective. The authors discover Chisel\u27s merits for realising synthesizable repetitive designs such as in SoC development, experiencing the benefits of Chisel\u27s object-oriented background in enhancing code maintainability and scalability, and implementation efficiency. However, the authors foresee that Chisel will compliment rather than replace traditional HDLs for RTL design applications due to its limitations in terms of behavioural modelling

Autotuning the Intel HLS Compiler using the Opentuner Framework

High level synthesis (HLS) tools can be used to improve design flow and decrease verification times for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design. The Intel HLS Compiler is a high level synthesis tool that takes in untimed C/C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. The translation does, however, require multiple iterations and manual optimizations to get comparable synthesized results to that of a solution written in a hardware descriptive language. The synthesis results can vary greatly based upon coding style and optimization techniques, and typically require an in-depth knowledge of FPGAs to fully optimize the translation which limits the audience of the tool. The extra abstraction that the C/C++ source code presents can also make it difficult to meet more specific design requirements; this includes designs to meet specific resource usage or performance based metrics. To improve the quality of results generated by the Intel HLS Compiler without a manual iterative process that requires an in-depth knowledge of FPGAs, this research proposes a method of automating some of the optimization techniques that improve the synthesized design through an autotuning process. The proposed approach utilizes the PyCParser library to parse C source files and the OpenTuner Framework to autotune the synthesis to provide a method that generates results that better meet the needs of the designer's requirements through lower FPGA resource usage or increased design performance. Such functionality is not currently available in Intel's commercial tools. The proposed approach was tested with the CHStone Benchmarking Suite of C programs as well as a standard digital signal processing finite impulse response filter. The results show that the commercial HLS tool can be automatically autotuned through placeholder injection using a source parsing tool for C code and using the OpenTuner Framework to autotune the results. For designs that are small in nature and include conducive structures to be autotuned, the results indicate resource usage reductions and/or performance increases of up to 40% as compared to the default Intel HLS Compiler results. The method developed in this research also allows additional design targets to be specified through the autotuner for consideration in the synthesized design which can yield results that are better matched to a design's requirements