Ein logisch-topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen

Es wird ein CAD-System ICAD-IC vorgestellt, das den Entwurf integrierter Schaltungen unterstützen soll. Der Kern des Systems besteht in einem Netzkalkül, der es erlaubt, neben der logischen Information auch geometrische Informationen zu handhaben. Dieser Kalkül besitzt verschiedene Ausprägungen, die den Entwurf auf verschiedenen Entwurfsebenen unterstützen. Das System ist um den Kalkül herum entwickelt, wie etwa ALGOL um die Numerik. Soweit das System bis jetzt entwickelt ist, betrifft es die logisch-topologische Entwurfsebene und den Übergang zur topographischen Entwurfsebene. Wir stellen hier das Konzept des Kalküls vor und erläutern an Beispielen einige Grundlagenuntersuchungen zu diesem Thema.We present a CAD-system \u27CAD-IC\u27, supporting the automatic design of integrated circuits. The kernel of the system is based on a "calculus of nets", which allows both, the handling of logical and geometrical information. Depending on the design-level different versions of this calculus may be adopted. The system itself is built around this calculus, as f.e. ALGOL around numerics. As far as the system is developed at the moment, it mainly deals with the logical-topological design level and the transition to the topographical level. We give the main ideas of the calculus and illustrate some basic investigations with help of examples

The pseudo-exhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced. Instead of test sets one applies pseudoexhaustive test sequences of a limited length, which provides well-known benefits as far as fault coverage, self-test capability, and simplicity of test generation are concerned. Some flip flops and latches are integrated into an incomplete scan path, such that each possible state of the circuit is reachable within a few steps. Some more flip flops and some new segmentation cells are added to the partial scan path in order to make a pseudoexhaustive test feasible. Algorithms for placing these devices automatically are presented. Also it is shown how to transform a pseudoexhaustive test set into a pseudoexhaustive test sequence of a similar size. The analyzed examples show that a conventional complete scan path without additional testability features requires more hardware overhead than the proposed test strategy, which retains all the known benefits of a pseudoexhaustive test

VLSI-Entwurfssystem (VENUS) fuer hoechstintegrierte CMOS-NMOS-Schaltungen (CAD fuer VLSI) Schlussbericht

With 53 figs., 9 tabs., 32 refs.TIB: FR 1341 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman