Using ant colony optimization for routing in microprocesors

Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers

Design framework for multifunctional additive manufacturing: placement and routing of three-dimensional printed circuit volumes

A framework for the design of additively manufactured (AM) multimaterial parts with embedded functional systems is presented (e.g., structure with electronic/electrical components and associated conductive paths). Two of the key strands of this proposed framework are placement and routing strategies, which consist of techniques to exploit the true-3D design freedoms of multifunctional AM (MFAM) to create 3D printed circuit volumes (PCVs). Example test cases are presented, which demonstrate the appropriateness and effectiveness of the proposed techniques. The aim of the proposed design framework is to enable exploitation of the rapidly developing capabilities of multimaterial AM

Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work

Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Transfer Level (RTL) level to form a suspected boundary consisting of multiple logics from one end to the other, layout to schematic mapping automation tool helps to identify fault in design within given boundary. Therefore the development of a path extractor program which is capable of extracting all possible paths from these start to end signals can save engineers time in tracing components involved between a fault line. This feature is extremely significant in Electronic Design Automation (EDA) as it can provide results of net name sequences stored in a database of mapper files. These mapper files can be used in layout design debug as the net sequence represents schematic signals. To be able to retrieve all possible signals involved within a suspected boundary is a popular search computational problem. Therefore the path extractor program proposed incorporates the characteristics of a depth-first search algorithm by considering the specifications of a cell-based design. The objectives achieved in this research are proven reliable with path extraction results consistent even with search depth manipulation. Performance differs an average of 12.6 % (iteration count) with keeping maximum allowable depth of search constant. Paths of net sequences were consistent throughout the verification of the path extractor program. This development and study of the path extract method carries significance in areas of EDA and debug diagnosis work

A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration

Quantum Annealing (QA) is an emerging technique, derived from Simulated Annealing, providing metaheuristics for multivariable optimisation problems. Studies have shown that it can be applied to solve NP-hard problems with faster convergence and better quality of result than other traditional heuristics, with potential applications in a variety of fields, from transport logistics to circuit synthesis and optimisation. In this paper, we present a hardware architecture implementing a QA-based solver for the Multidimensional Knapsack Problem, designed to improve the performance of the algorithm by exploiting parallelised computation. We synthesised the architecture using as a target an Altera FPGA board and simulated the execution for solving a set of benchmarks available in the literature. Simulation results show that the proposed implementation is about 100 times faster than a single-thread general-purpose CPU without impact on the accuracy of the solution

Design Optimization Strategy for Multifunctional 3D Printing

An optimization based design methodology for the additive manufacture of multifunctional parts (for example, a structure with embedded electronic/electrical systems and associated conductive paths) is presented. This work introduces a coupled optimization strategy where Topology Optimization (TO) is combined with an automated placement and routing approach that enables determination of an efficient internal system configuration. This permits the effect of the incorporation of the internal system on the structural response of the part to be taken into account and therefore enables the overall optimization of the structure-system unit. An example test case is included in the paper to evaluate the optimization strategy and demonstrate the methods effectiveness. The capability of this method allows the exploitation of the manufacturing capability under development within the Additive Manufacturing (AM) community to produce 3D internal systems within complex structures.Mechanical Engineerin

Exploring Spin-transfer-torque devices and memristors for logic and memory applications

As scaling CMOS devices is approaching its physical limits, researchers have begun exploring newer devices and architectures to replace CMOS. Due to their non-volatility and high density, Spin Transfer Torque (STT) devices are among the most prominent candidates for logic and memory applications. In this research, we first considered a new logic style called All Spin Logic (ASL). Despite its advantages, ASL consumes a large amount of static power; thus, several optimizations can be performed to address this issue. We developed a systematic methodology to perform the optimizations to ensure stable operation of ASL. Second, we investigated reliable design of STT-MRAM bit-cells and addressed the conflicting read and write requirements, which results in overdesign of the bit-cells. Further, a Device/Circuit/Architecture co-design framework was developed to optimize the STT-MRAM devices by exploring the design space through jointly considering yield enhancement techniques at different levels of abstraction. Recent advancements in the development of memristive devices have opened new opportunities for hardware implementation of non-Boolean computing. To this end, the suitability of memristive devices for swarm intelligence algorithms has enabled researchers to solve a maze in hardware. In this research, we utilized swarm intelligence of memristive networks to perform image edge detection. First, we proposed a hardware-friendly algorithm for image edge detection based on ant colony. Next, we designed the image edge detection algorithm using memristive networks

The single row layout problem with clearances

The single row layout problem (SRLP) is a specially structured instance of the classical facility layout problem, especially used in flexible manufacturing systems. The SRLP consists of finding the most efficient arrangement of a given number of machines along one side of the material handling path with the purpose of minimising the total weighted sum of distances among all machine pairs. To reflect real manufacturing situations, a minimum space (so-called clearances) between machines may be required by observing technological constraints, safety considerations and regulations. This thesis intends to outline the different concepts of clearances used in literature and analyse their effects on modelling and solution approaches for the SRLP. In particular the special characteristics of sequence-dependent, asymmetric clearances are discussed and finally extended to large size clearances (machine-spanning clearances). For this, adjusted and novel model formulations and solution approaches are presented. Furthermore, a comprehensive survey of articles published in this research area since 2000 is provided which identify recent developments and emerging trends in SRLP