A knowledge-based approach to VLSI-design in an open CAD-environment

A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI technique can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge - strategic and task-specific - in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design

VLSI Architecture and Design

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible. The cost of communication will make designs enforcing locality superior to other types of designs. Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity. With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers"

Developing VLSI Curricula in Electrical and Computer Engineering Department

© ASEE 2010VLSI (Very Large Scale Integrated Circuits) technology has enabled the information technology revolution which greatly changed the life style of human society. Computers, internet, cellphones, digital cameras/camcorders and many other consumer electronic products are powered by VLSI technology. In the past decades, the VLSI industry was constantly driven by the miniaturization of transistors. As governed by Moore’s law, the number of transistors in the same chip area has been doubled every 12 to 18 months. Nowadays, a typical VLSI CPU chip can contain millions to billions of transistors. As a result, the design of VLSI system is becoming more and more complex. Various EDA tools must be used to help the design of modern VLSI chips. The semiconductor and VLSI industry remain strong needs for VLSI engineers each year. In this paper, efforts in developing systematic VLSI curricula in Electrical and Computer Engineering department have been proposed. The goal of the curricula is to prepare students to satisfy the growing demands of VLSI industry as well as the higher education/research institutions. Modern VLSI design needs a thorough understanding about VLSI in device, gate, module and system levels. We developed CPEG/EE 448D: Introduction to VLSI to give students a comprehensive introduction about digital VLSI design and analysis. In this course, various EDA tools (such as Mentor Graphics tools, Cadence PSPICE, Synopsys) are used in the course projects to help students practice the VLSI design. In addition, analog and mixed signal circuit design are becoming more and more important as MEMS (Microelectromechanical Systems) and Nano devices are integrated with VLSI into Systemon-Chip (SoC) design. We developed CPEG/EE 458: Analog VLSI to introduce the analog and mixed signal VLSI design. As portable electronics (e.g. laptops, cellphones, PDAs, digital cameras) becoming more and more popular, low power VLSI circuit design is becoming a hot field. We developed CPEG/EE 548: Low Power VLSI Circuit Design to introduce various low power techniques to reduce the power consumption of VLSI circuits. Nowadays the VLSI circuits can contain billions of transistors, the testing of such complex system becoming more and more challenging. We developed CPEG/EE 549: VLSI Testing to introduce various VLSI testing strategies for modern VLSI design. In addition to the design and testing, we also developed EE 448: Microelectronic Fabrication to introduce the fabrication processes of modern VLSI circuits. With such a series of VLSI related curricula, students have an opportunity to learn comprehensive knowledge and hands-on experience about VLSI circuit design, testing, fabrication and EDA tools. Students demonstrate tremendous interests in the VLSI field, and all the VLSI courses are generally oversubscripted by students in the early stage of enrollment. Many students are also doing the VLSI graduate research and published various papers/posters in the VLSI related journals/conferences

Architecture for VLSI design of Reed-Solomon encoders

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature

A procedural method for the efficient implementation of full-custom VLSI designs

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system

Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described

VLSI top-down design based on the separation of hierarchies

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified by an experimental self-timed CMOS RISC computer design