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Analysis and Optimization of Graphene FET based Nanoelectronic Integrated Circuits
Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon.
Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics.
The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm.
In summary, the dissertation is to expected to aid the state of the art in following ways:
1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with.
2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization.
3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well
Opportunities for radio frequency nanoelectronic integrated circuits using carbon-based technologies
This thesis presents a body of work on the modeling of and performance predictions for carbon nanotube field-effect transistors (CNFET) and graphene field-effect transistors (GFET). While conventional silicon-based CMOS is expected to reach its ultimate scaling limits during the next decade, these two novel technologies are promising candidates for future high-performance electronics. The main goal of this work is to investigate
on the opportunities of using such carbon-based electronics for RF integrated circuits.
This thesis addresses 1) the modeling of noise and process variability in CNFETs, 2) RF performance predictions for CNFETs, and 3) an accurate GFET compact model. This work proposes the first CNFET noise compact model. Noise is of primary importance for RF applications and its description significantly increases the insight gained from simulation studies. Furthermore, a CNFET variability model is presented, which handles tube synthesis and metal tube removal imperfections. These two model extensions have been added to the Stanford CNFET compact model and allow for the variability-aware RF performance assessment of the CNFET technology.
In continuation, comprehensive RF performance projections for CNFETs are provided both on the device and circuit level. The overall set of ITRS RF-CMOS technology requirement FoMs is determined and shows that the CNFET performs excellently in terms of speed, gain, and minimum noise figure. Furthermore, for the first time FoMs are reported for the basic RF building blocks low-noise amplifier and oscillator. In addition, it is shown that CNFET downscaling yields significant performance improvements. Based on these analyses it is confirmed that the CNFET has the potential to outperform Si-CMOS in RF applications.
A third key contribution of this thesis is the development of an accurate GFET compact model. Previous compact models simplify several physical aspects, which can cause erroneous simulation results. Here, an accurate yet simple mathematical description of the GFET’s current-voltage relation is proposed and implemented in Verilog-A. Comprehensive error analyses are done in order to highlight the advantages of the new approach.
Furthermore, the model is verified against measurement results. The developed GFET model is an important step towards better understanding the characteristics and opportunities of graphene-based analog circuitry