A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

Ultra-Wide-Band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB System-on-Chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging metho

Energy Detection UWB Receiver Design using a Multi-resolution VHDL-AMS Description

Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations

An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip

The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies. We propose a layered approach based on VHDL-AMS for the first design stages and on an intelligent use of a circuit-level simulator for the transistor-level phase. We apply the latter just to one block at a time and wrap it within the system-level VHDL-AMS description. This method allows to capture the impact of circuit-level design choices and non-idealities on system performance. To demonstrate the effectiveness of the methodology we show how the refinement of the design affects specific UWB system parameters such as bit-error rate and localization estimations

A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems

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Development of a Multi-Standard Protocol Using Software Defined Radio for a Mobile Station Transceiver

In this thesis, the Software Defined Radio Digital Control System (SDR DCS) has been developed to perform a multi-standard protocol of the handset using the GSM and CDMA systems. The SDR DCS was designed for the SDR based band digital transceiver of the handset as a control and protocol software to control and handle the operation of the handset when roaming between different protocols; it could easily and quickly let the handset reconfigure with the future protocol; it configured the handset with either of the GSM or CDMA protocol software, and scheduled for reconfiguration of the handset with the second protocol in sequence. The SDR DCS controls the download of the specific air interface environment. In order to implement the whole design in software, the design had to go through three stages. The first stage was to do all the design steps in the software using generic computing resources such as Hardware Description Language (HDL), with the top-level design for each protocol. The second stage was to define a logic circuit to perform the signal processing for each protocol; this step was applied after the simulation and synthesis, and eventually programming that circuit into the FPGA board. The third stage was to use the FPGA to implement the functions required for each protocol which constitutes the multi-standard protocol. The VHDL files were created for each element of the GSM and CDMA protocols. The GSM related system was developed with encoders and decoders linked to the channel model. The CDMA related system was designed with a transmitter to encode the user’s data into wide bandwidth using a reverse link channel and a synchronized receiver to receive the signal from the forward link channel and decode the wide bandwidth to recover the base band user’s data. The Synopsys™ software package was used for the design, synthesis and simulation of the SDR base band platform. The simulation tools used include the Model Sim and System Studio. Meanwhile, the Xilinx ISE 9.2i was used as the synthesis tool. The results of the simulated and synthesized top-level design files were downloaded into the Xilinx XSA-3S1000 FPGA board. The waveforms for the GSM and CDMA outputs approximately matched the ones seen in the oscilloscope for the FPGA output pin. This proved that the SDR DCS had successfully implemented its task, according to the objectives of the design

Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels

This thesis combines Keysight’s SystemVue software with a Vector Signal Analyzer (VSA) and Vector Signal Generator (VSG) to test receiver equalization schemes over physical channels. The testing setup, “Equalization Verification,” is intended to be able to evaluate any equalization scheme over any physical channel, and a decision-directed feed-forward LMS equalizer is used as an example. The decision-directed feed-forward LMS equalizer is shown to decrease the BER from 10-2 to 10-3 (average of all trials) over a CAT7 and CAT6A cable, both simulated and physical, for 1GHz and 2GHz carrier, and 80MHz data rate. A wireless channel, 2.4GHz Dipole Antenna, is also tested to show that the addition of the equalization scheme decreases BER from 10-5 to less than 10-5. Then the simulation and equalization parameters (LMS step size, PRBS, etc.) are changed to further verify the equalization scheme. The simulated channel BER results do not always match the physical channel BER results, but the equalization scheme does decrease BER for both wired and wireless channels. Then transistor-based equalization model is created using both HDL SystemVue components and blocks easily implemented by transistors. The model is then verified using HDL, Spice, and SystemVue simulation. Overall this thesis accomplishes its goal of creating a testing setup, Equalization Verification, to show that adding a given simulated equalization scheme in SystemVue can improve the quality of the link, by decreasing BER by at least an order of magnitude, over a specific physical channel

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation