Compiler and Architecture Design for Coarse-Grained Programmable Accelerators

abstract: The holy grail of computer hardware across all market segments has been to sustain performance improvement at the same pace as silicon technology scales. As the technology scales and the size of transistors shrinks, the power consumption and energy usage per transistor decrease. On the other hand, the transistor density increases significantly by technology scaling. Due to technology factors, the reduction in power consumption per transistor is not sufficient to offset the increase in power consumption per unit area. Therefore, to improve performance, increasing energy-efficiency must be addressed at all design levels from circuit level to application and algorithm levels. At architectural level, one promising approach is to populate the system with hardware accelerators each optimized for a specific task. One drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low as they perform one specific function. Using software programmable accelerators is an alternative approach to achieve high energy-efficiency and programmability. Due to intrinsic characteristics of software accelerators, they can exploit both instruction level parallelism and data level parallelism. Coarse-Grained Reconfigurable Architecture (CGRA) is a software programmable accelerator consists of a number of word-level functional units. Motivated by promising characteristics of software programmable accelerators, the potentials of CGRAs in future computing platforms is studied and an end-to-end CGRA research framework is developed. This framework consists of three different aspects: CGRA architectural design, integration in a computing system, and CGRA compiler. First, the design and implementation of a CGRA and its instruction set is presented. This design is then modeled in a cycle accurate system simulator. The simulation platform enables us to investigate several problems associated with a CGRA when it is deployed as an accelerator in a computing system. Next, the problem of mapping a compute intensive region of a program to CGRAs is formulated. From this formulation, several efficient algorithms are developed which effectively utilize CGRA scarce resources very well to minimize the running time of input applications. Finally, these mapping algorithms are integrated in a compiler framework to construct a compiler for CGRADissertation/ThesisDoctoral Dissertation Computer Science 201

Configuration Recognition, Communication Fault Tolerance and Self-reassembly for the CKBot

We present and experimentally verify novel methods for increasing the generality of control, autonomy and reliability for modular robotic systems. In particular, we demonstrate configuration recognition, distributed communication fault tolerance, and the organization and control of self-reassembly with the Connector Kinetic roBot (CKBot). The primary contribution of this work is the presentation and experimental verification of these innovative methods that are general and applicable to other modular robotic systems. We describe our CKBot system and compare it to other similar, state-of-the-art modular robotic systems. Our description and comparison highlights various design developments, features, and notable achievements of these systems. We present work on isomorphic configuration recognition with CKBot. Here, we utilize basic principles from graph theory to create and implement an algorithm on CKBot that automatically recognizes modular robot configurations. In particular, we describe how comparing graph spectra of configuration matrices can be used to find a permutation matrix that maps a given configuration to a known one. If a configuration is matched to one in a library of stored gaits, a permutation mapping is applied and the corresponding coordinated control for locomotion is executed. An implementation of the matching algorithm with small configurations of CKBot configurations that can be rearranged during runtime is presented. We also present work on a distributed fault-tolerance algorithm used to control CKBot configurations. Here, we use a triple modular redundancy approach for CKBot units to collectively vote on observations and execute commands in the presence of infrared (IR) communication failures. In our implementation, we broadcast infrared signals to modules which collaboratively vote on a majority course of action. Various gait selections for a seven module caterpillar and sixteen module quadruped with faulty subsets of IR receivers have been verified to demonstrate the algorithm\u27s robustness. Lastly, we present work on the communication hierarchy and control state machine for the Self-reassembly After Explosion (SAE) robot. Here, we discuss the interaction and integration of the various sensory inputs and control outputs implemented for camera-guided self-reassembly with CKBot. This section describes the overall communication system and reassembly sequence planning after a group of CKBot clusters is kicked apart

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure