6 research outputs found
The Computational Power of Distributed Shared-Memory Models with Bounded-Size Registers
The celebrated Asynchronous Computability Theorem of Herlihy and Shavit (STOC
1993 and STOC 1994) provided a topological characterization of the tasks that
are solvable in a distributed system where processes are communicating by
writing and reading shared registers, and where any number of processes can
fail by crashing. However, this characterization assumes the use of
full-information protocols, that is, protocols in which each time any of the
processes writes in the shared memory, it communicates everything it learned
since the beginning of the execution. Thus, the characterization implicitly
assumes that each register in the shared memory is of unbounded size. Whether
unbounded size registers are unavoidable for the model of computation to be
universal is the central question studied in this paper. Specifically, is any
task that is solvable using unbounded registers solvable using registers of
bounded size? More generally, when at most processes can crash, is the
model with bounded size registers universal? These are the questions answered
in this paper
Progress-Space Tradeoffs in Single-Writer Memory Implementations
Many algorithms designed for shared-memory distributed systems assume the single-writer multi- reader (SWMR) setting where each process is provided with a unique register that can only be written by the process and read by all. In a system where computation is performed by a bounded number n of processes coming from a large (possibly unbounded) set of potential participants, the assumption of an SWMR memory is no longer reasonable. If only a bounded number of multi- writer multi-reader (MWMR) registers are provided, we cannot rely on an a priori assignment of processes to registers. In this setting, implementing an SWMR memory, or equivalently, ensuring stable writes (i.e., every written value persists in the memory), is desirable.
In this paper, we propose an SWMR implementation that adapts the number of MWMR registers used to the desired progress condition. For any given k from 1 to n, we present an algorithm that uses n + k ? 1 registers to implement a k-lock-free SWMR memory. In the special case of 2-lock-freedom, we also give a matching lower bound of n + 1 registers, which supports our conjecture that the algorithm is space-optimal. Our lower bound holds for the strictly weaker progress condition of 2-obstruction-freedom, which suggests that the space complexity for k-obstruction-free and k-lock-free SWMR implementations might coincide
Allocation adaptative de registres en utilisant un nombre linéaire de registres
International audienceOn présente un algorithme adaptatif dans lequel les processus utilisent des registres multi écrivains multi lecteurs. Cet algorithme permet à chaque processus d'obtenir un accès exclusif à un registre dont il sera l'écrivain unique et que tous les processus pourront lire. L'algorithme est adaptatif : il ne connait pas a priori le nombre de processus qui vont demander un accés exclusif en écriture à un registre. C'est le premier algorithme permettant d'obtenir ce résultat en utilisant des registres dont le nombre est une fonction linéaire du nombre de participants. Les précédents algorithmes adaptatifs utilisent au moins Theta(n^{3/2}) registres
Allocation adaptative de registres en utilisant un nombre linéaire de registres
International audienceOn présente un algorithme adaptatif dans lequel les processus utilisent des registres multi écrivains multi lecteurs. Cet algorithme permet à chaque processus d'obtenir un accès exclusif à un registre dont il sera l'écrivain unique et que tous les processus pourront lire. L'algorithme est adaptatif : il ne connait pas a priori le nombre de processus qui vont demander un accés exclusif en écriture à un registre. C'est le premier algorithme permettant d'obtenir ce résultat en utilisant des registres dont le nombre est une fonction linéaire du nombre de participants. Les précédents algorithmes adaptatifs utilisent au moins Theta(n^{3/2}) registres
Resilience-Building Technologies: State of Knowledge -- ReSIST NoE Deliverable D12
This document is the first product of work package WP2, "Resilience-building and -scaling technologies", in the programme of jointly executed research (JER) of the ReSIST Network of Excellenc