Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations

The current design and manufacturing semiconductor technologies require to test the products against delay related defects. However, complex acpSOC require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these acpSOC because the test application requires only one storage element per scan cell. Compressed skewed-load test generator based on genetic algorithm is proposed for wrapper-based logic cores of acpSOC. Deterministic population initialization is used to ensure the highest achievable aclTDF coverage for the given wrapper and scan cell order. The developed method performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods

Multi-Cycle Test with Partial Observation on Scan-Based BIST Structure

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation.2011 Asian Test Symposium (ATS), 20-23 Nov. 2011, New Delhi, Indi

Improving timing verification and delay testing methodologies for IC designs

textThe task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceElectrical and Computer Engineerin

Enhancement and validation of a test technique for integrated circuits

This thesis focuses on a scan-based delay testing technique that was recently developed at ETS. This new approach, called Captureless Delay Testing (CDT), has been proposed as a technique that complements traditional methods of test, ensuring the integrated circuits will function at their proposed clock speed, further improving the test coverage of the particular type of test. Furthermore, CDT incorporates the use of sensors enabling the detection of the presence of transitions at strategic locations. The purpose of this project is to improve on certain aspects of this novel technique. At first, we analyze the delay distribution of the non-covered nodes by traditional methods of test, in order to develop the best way possible of placement of the CDT sensors. We present, using Perl Language, the ensemble of tools developed for this purpose. The end results obtained confirm that the paths that pass through the non-covered nodes are longer than those that traverse the covered ones. The difference between the two types of paths exceeds 20%) of the clock period when considering the shorter path delay values. Secondly, we propose a fially automated algorithm that enables, at the earliest stages of the test vectors generation process: 1) the identification of the non-covered nodes, 2) the identification of the placements of the CDT sensors at the inputs of the flip-flops for further improvement of the test coverage, and 3) the minimization of the number of sensors with regards to requirements. Our results indicate that when we apply CDT on top of transitionbased fault model we can improve the test coverage by 5%. Moreover, the algorithm of CDT sensors minimization allows a reduction of more than 85% the number of those sensors with a minimal test coverage loss, on average of 1.6%

Fault simulation and test generation for small delay faults

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which models delay faults caused by the combination of spot defects and parametric process variation. According to the new model, a realistic delay fault coverage metric has been developed. Traditional path delay fault coverage metrics result in unrealistically low fault coverage, and the real test quality is not reflected. The new metric uses a statistical approach and the simulation based fault coverage is consistent with silicon data. Fast simulation algorithms are also included in this dissertation. The new metric suggests that testing the K longest paths per gate (KLPG) has high detection probability for small delay faults under process variation. In this dissertation, a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate for both combinational and sequential circuits is presented. Many techniques are used to reduce search space and CPU time significantly. Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288. The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches

Abstracts of manuscripts submitted in 1989 for publication

This volume contains the abstracts of manuscripts submitted for publication during calendar year 1989 by the staff and students of the Woods Hole Oceanographic Institution. We identify the journal of those manuscripts which are in press or have been published. The volume is intended to be informative, but not a bibliography. The abstracts are listed by title in the Table of Contents and are grouped into one of our five deparments, marine policy, or the student category. An author index is presented in the back to facilitate locating specific papers

NDT for the diagnosis of modern, historical and archaeological structures

This thesis has been developed with the aim to explore thoroughly potential and limit of the GPR and ERT methods for monitoring heterogeneous structures where different construction materials are combined together. Firstly we analysed the GPR response, in various construction materials related to different modern, historical or archaeological structures. In particular, three real examples were investigated during the thesis, namely: the Pyramid of Caius Cestius, the Passage of Commodus and the Colle Oppio Ninpheum, all in Rome. According to the different types of material and frequency antennas, different GPR responses and therefore dissimilar degree of resolution and of attenuation was obtained. In light of this, the interposition between the surface of the investigated medium and the GPR antenna of a dielectric material (e.g. Plexiglas) was performed in order to improve the resolution. Furthermore, an application of the GPR and ERT methods for monitoring a load test executed on masonry samples was presented. This panels were built up in the laboratory controlled conditions using tuff and bricks (widespread materials employed in Italy for decades for masonry buildings) and also were reproduced in the phase of theoretical modeling. The laboratory samples are reinforced with a conductive fibre fabric, where a high-conductive material (steel wires) is combined together with a dielectric material (basalt fibre). In order to improve the sample-antenna coupling in the presence of conductive reinforcements, a Plexiglas (polimetilmetacrilato - PMMA) plate was added underneath a 2 GHz antenna. GPR data were acquired along profiles spaced 0.1 m apart and ERT measurements were executed on a 0.1 m regular spaced grid with a dipole-dipole array operating in a three-dimensional configuration. GPR datasets were also analysed in non-conventional mode, by means of the picking of the reflection time of the EM wave from the rear face of the wall samples. Results show that GPR and electrical resistivity tomography were both able to detect fractures and weakness zones caused by the load application, even though with a higher resolution for the georadar with respect to the geoelectrical method. Moreover, mapping the GPR data in terms of the dielectric constant and mean absolute amplitude is particularly diagnostic to detect the effective fracturing pattern, after the application of the diagonal load. Therefore, GPR and ERT methods can reduce the degree of uncertainty in the detection of fractures, voids or cavities, with respect to the standard processing, by the combined analysis of radargrams, time-slices and resistivity ERT models. Furthermore, for the GPR laboratory data acquired directly on the reinforced face of samples, it is demonstrated how interposing a layer of dielectric material between the antenna and the structure can substantially improve the antenna coupling and consequently the capability to detect fractures and to reach the rear face of the sample, despite losing resolution in the case of shallow high-conductive layers. Finally, three-dimensional synthetic simulations on the same samples validate the experimental evidences. Therefore, we demonstrate that this approach can be a reliable tool to monitor static load tests and it can be further extended to the whole load cycle (before, during and after the experiment)