Weak Inversion Performance of CMOS and DCVSPG Logic Families in Sub-300mV Range

In this paper the advantages of using Differential Cascode Voltage Switch Pass Gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and Energy-Delay-Product (EDP) figures. Multiple gates were simulated using 0.18µm standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts

Pico-Watt Source-Coupled Logic Circuits

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on different digital building blocks are provided to validate the main concepts presented in this paper. Implemented in conventional 0.18um CMOS technology, the bias current of each STSCL gate can be reduced below 10pA, which corresponds to a power-delay product (PDP) of less than 500aJ

Analysis and mitigation of variability in subthreshold design

Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramati-cally increased sensitivity to process variations due to the exponen-tial relationship of subthreshold drive current with Vth variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical mod-els against Monte Carlo SPICE simulations and show that they accu-rately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs

A sub-threshold cell library and methodology

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 97-102).Sub-threshold operation is a compelling approach for energy-constrained applications where speed is of secondary concern, but increased sensitivity to process variation must be mitigated in this regime. With scaling of process technologies, random within-die variation has recently introduced another degree of complexity in circuit design. This thesis proposes approaches to mitigate process variation in sub-threshold circuits through device sizing, topology selection and fault-tolerant architecture. This thesis makes several contributions to a sub-threshold circuit design methodology. A formal analysis of device sizing trade-offs between delay, energy, and variability reveals that while minimum size devices provide lowest energy and delay in sub-threshold, their increased sensitivity to random dopant fluctuation may cause functional errors. A proposed variation-driven design approach enables consistent sizing of logic gates and registers for constant functional yield. A yield constraint imposes energy overhead at low power supply voltages and changes the minimum energy operating point of a circuit.(cont.) The optimal supply and device sizing depend on the topology of the circuit and its energy versus VDD characteristic. The analysis resulted in a 56-cell library in 65nm CMOS, which is incorporated in a computer-aided design flow. A test chip synthesized from this library implements a fault-tolerant FIR filter. Algorithmic error detection enables correction of transient timing errors due to delay variability in sub-threshold, and also allows the system frequency to be set more aggressively for the average case instead of the worst case.by Joyce Y.S. Kwong.S.M

Ultra Low Power SubThreshold Device Design Using New Ion Implantation Profile

Title from PDF of title page, viewed August 14, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 92-97)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016One of the important aspects of integrated circuit design is doping profile of a transistor along its length, width and depth. Devices for super-threshold circuit usually employ halo and retrograde doping profiles in the channel to eliminate many unwanted effects like DIBL, short channel effect, threshold variation etc. These effects are always become a serious issue whenever circuit operates at higher supply voltage. Subthreshold circuit operates at lower supply voltage and these kind of effects will not be a serious issue. Since subthreshold circuit will operate at much lower supply voltage then devices for subthreshold circuit does not require halo and retrograde doping profiles. This will reduce the number of steps in the fabrication process, the parasitic capacitance and the substrate noise dramatically. This dissertation introduces four new doping profiles for devices to be used in the ultra low-power subthreshold circuits. The proposed scheme addresses doping variations along all the dimensions (length, width and depth) of the device. Therefore, the approaches are three dimensional (3D) in nature. This new doping scheme proposes to employ Gaussian distribution of doping concentration along the length of the channel with highest concentration at the middle of the channel. The doping concentration across the depth of the device from the channel region towards the bulk of the device can follow one of the following four distributions: (a) exponentially decreasing, (b) Gaussian, (c) low to high, and (d) uniform doping. The proposed doping scheme keeps the doping concentration along the width of the device uniform. Therefore, under this scheme we achieve four sets of new 3D doping profiles. This dissertation also introduces a new comprehensive doping scheme for the transistors in subthreshold circuits. The proposed doping scheme would bring doping changes in the source and drain areas along with the substrate and channel region of the transistors. The proposed doping scheme is characterized by the absence of halos at the source and drain end. We propose a Gaussian doping distribution inside the source, drain region and a low-high-low distribution across the depth of the transistor from the channel surface towards the body region. It also has a low-high-low doping distribution along the length of the transistor below the channel region. Results show that a device optimized with proposed doping profiles would offer higher ON current in the subthreshold region than a device with the conventional halo and retrograde doping profiles. Among the four 3D doping profiles for subthreshold device some has better ON current than others. Based on specific requirements one of these four doping profiles can be adopted for different ultra-low-power applications. Our analysis shows better subthreshold swing can be achieved using new doping profile based subthreshold design. Results also show that the optimized device with the proposed comprehensive doping profile would provide higher ON current (Iₒₙ) at smaller body bias condition. The analysis is performed by changing the doping profile, body bias and (Vgs) to observe the off-state current (Iₒff), threshold voltage variation, magnitude of Iₒₙ/Iₒff ratio, transconductance and the output conductance with the proposed doping profiles.Introduction -- Subthreshold background -- Implantation profiles -- Threshold voltage calculation -- Comprehensive implantation profile -- Conclusion and future workxvi, 98 page