Performance analysis of Dual Material Gate (DMG) Silicon on Insulator (SOI) tunnel fets

As modern day computing systems are designed to perform innumerable number of functions with tremendous speed, the number of circuits to be accommodated in a chip keeps increasing day by day. Hence electronics industry constantly faces the challenge of miniaturization of transistors to increase the package density and thus linear scaling of CMOS technology has become a necessity in the present day microelectronic and nano-electronic regime. This leads to a major crisis of static power consumption and hence conventional MOSFETs fail to be a suitable candidate to handle the situation. Also Short Channel Effects(SCEs) come into picture. So non-conventional devices started gaining its significance to meet the ITRS requirements. A promising candidate that attracted attention was Tunnel FETs which are gated reverse biased p-i-n diodes where ON current would be due to band-to-band tunneling and they exhibit very low OFF current of 10-17 A/µm which makes them a potential solution for power crisis. Also they prove to be an energy efficient electronic switch with a subthreshold swing not limited to 60mV/decade. Negligible Short Channel Effects of these devices gives them an added advantage over conventional MOSFETs .All these features raise up Tunnel FET as superior candidate for future CMOS era. In the presented work, an analysis into the performance of a Dual Material Gate Single Dielectric SOI Tunnel FET has been done. Numerous simulations were done to determine the influence of work functions of both the gate materials on the electrical characteristics of the device. Comparative study was done between Dual Material Gate device and Single Material Gate device with regards to their electrical characteristics as well as SCEs like Drain Induced Barrier Lowering(DIBL) and threshold voltage roll-off. Parameters like intrinsic capacitances as well as transconductances were also determined

Energy efficient core designs for upcoming process technologies

Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are being actively explored to extend the march in increasing the computational power and efficiency. It is essential for computer architects to understand the opportunities and challenges in utilizing the upcoming process technology trends in order to design the most efficient processors. In this work, we consider three process technology trends and propose core designs that are best suited for each of the technologies. The process technologies are expected to be viable over a span of timelines. We first consider the most popular method currently available to improve the energy efficiency, i.e. by lowering the operating voltage. We make key observations regarding the limiting factors in scaling down the operating voltage for general purpose high performance processors. Later, we propose our novel core design, ScalCore, one that can work in high performance mode at nominal Vdd, and in a very energy-efficient mode at low Vdd. The resulting core design can operate at much lower voltages providing higher parallel performance while consuming lower energy. While lowering Vdd improves the energy efficiency, CMOS devices are fundamentally limited in their low voltage operation. Therefore, we next consider an upcoming device technology -- Tunneling Field-Effect Transistors (TFETs), that is expected to supplement CMOS device technology in the near future. TFETs can attain much higher energy efficiency than CMOS at low voltages. However, their performance saturates at high voltages and, therefore, cannot entirely replace CMOS when high performance is needed. Ideally, we desire a core that is as energy-efficient as TFET and provides as much performance as CMOS. To reach this goal, we characterize the TFET device behavior for core design and judiciously integrate TFET units, CMOS units in a single core. The resulting core, called HetCore, can provide very high energy efficiency while limiting the slowdown when compared to a CMOS core. Finally, we analyze Monolithic 3D (M3D) integration technology that is widely considered to be the only way to integrate more transistors on a chip. We present the first analysis of the architectural implications of using M3D for core design and show how to partition the core across different layers. We also address one of the key challenges in realizing the technology, namely, the top layer performance degradation. We propose a critical path based partitioning for logic stages and asymmetric bit/port partitioning for storage stages. The result is a core that performs nearly as well as a core without any top layer slowdown. When compared to a 2D baseline design, an M3D core not only provides much higher performance, it also reduces the energy consumption at the same time. In summary, this thesis addresses one of the fundamental challenges in computer architecture -- overcoming the fact that CMOS is not scaling anymore. As we increase the computing power on a single chip, our ability to power the entire chip keeps decreasing. This thesis proposes three solutions aimed at solving this problem over different timelines. Across all our solutions, we improve energy efficiency without compromising the performance of the core. As a result, we are able to operate twice as many cores with in the same power budget as regular cores, significantly alleviating the problem of dark silicon