A logic-based approach for the verification of UML timed models

This article presents a novel technique to formally verify models of real-time systems captured through a set of heterogeneous UML diagrams. The technique is based on the following key elements: (i) a subset of Unified Modeling Language (UML) diagrams, called Coretto UML (C-UML), which allows designers to describe the components of the system and their behavior through several kinds of diagrams (e.g., state machine diagrams, sequence diagrams, activity diagrams, interaction overview diagrams), and stereotypes taken from the UML Profile for Modeling and Analysis of Real-Time and Embedded Systems; (ii) a formal semantics of C-UML diagrams, defined through formulae of the metric temporal logic Tempo Reale ImplicitO (TRIO); and (iii) a tool, called Corretto, which implements the aforementioned semantics and allows users to carry out formal verification tasks on modeled systems. We validate the feasibility of our approach through a set of different case studies, taken from both the academic and the industrial domain

TURTLE-P: a UML profile for the formal validation of critical and distributed systems

The timed UML and RT-LOTOS environment, or TURTLE for short, extends UML class and activity diagrams with composition and temporal operators. TURTLE is a real-time UML profile with a formal semantics expressed in RT-LOTOS. Further, it is supported by a formal validation toolkit. This paper introduces TURTLE-P, an extended profile no longer restricted to the abstract modeling of distributed systems. Indeed, TURTLE-P addresses the concrete descriptions of communication architectures, including quality of service parameters (delay, jitter, etc.). This new profile enables co-design of hardware and software components with extended UML component and deployment diagrams. Properties of these diagrams can be evaluated and/or validated thanks to the formal semantics given in RT-LOTOS. The application of TURTLE-P is illustrated with a telecommunication satellite system

The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.

The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems

Modeling and analysis of real-time software systems using UML

Real-Time Systems (RTS) should not only function correctly but should also satisfy time constraints. RTS include embedded systems, which are used nowadays in a variety of applications. These are, for instance, house appliances, automotive, aeronautic/aerospace, and health monitoring systems, to mention just a few. The design of such systems is complex and challenging. In order to cope with the complexity of RTS, there is shift in their development to follow a model-driven approach, such as the Model Driven Architecture (MDA), which relies on using models of high level of abstraction. The Unified Modeling Language (UML) is the Object Management Group (OMG) standard modeling language to support MDA. UML is appropriate for software systems because it allows for a multi-view modeling approach through its multitude of diagrams covering the structure, the behavior and the deployment architecture. Moreover, UML is also used in the domain of real-time software systems. This is achieved through its profiles, including, the OMG standard profile for Schedulability, Performance and Time (UML/SPT) or the upcoming standard UML Profile for Modeling and Analysis of Real-Time and Embedded Systems (MARTE). However, UML modeling faces some challenging issues such as model consistency. This issue becomes worse in the context of real-time software systems because additional aspects should be taken into consideration, including time, concurrency and schedulability. In this thesis, we address several issues related to modeling and validation of RTS with UML. We focus in particular on the consistency of UML/SPT models. We adopt an incremental approach to check the consistency of these models by distinguishing the syntactic and semantic levels. The latter is further decomposed into behavioral, concurrency-related and time consistency. Our contributions in this thesis are fourfold. First, we leverage the extensibility mechanisms of UML to propose an extension to UML/SPT. This extension enables the modeling of multicast communications, which is required for the description of the behavior of certain real-time protocols. Second, we propose a formalization of the concurrency modeling capability in UML/SPT using timed automata. This formal semantics allows for applying well-established model checking techniques to check concurrency related consistency in UML/SPT models. Third, we propose an MDA-compliant approach to enable schedulability analysis of UML/SPT models. We present a proof of concept for this approach through a prototype implementation using the Atlas Transformation Language (ATL) and XML-based technologies. Finally, we use the schedulability analysis applied to UML/SPT models in order to check the time consistency of a system design modeled by means of a set of state machines with respect to time constraints modeled using a set of sequence diagrams annotated with UML/SPT time stereotypes. Keywords : Real-time systems, Model-driven Architecture, UML, UML/SPT, Model transformation, ATL, XML, XSLT, Consistency, Concurrency, Model Checking, Schedulability Analysis

Extending UML-RT for Control System Modelling

There is a growing interest in adopting object technologies for the development of real-time control systems. Several commercial tools, currently available, provide object-oriented modeling and design support for real-time control systems. While these products provide many useful facilities, such as visualization tools and automatic code generation, they are all weak in addressing the central characteristic of real-time control systems design, i.e., providing support for a designer to reason about timeliness properties. We believe an approach that integrates the advancements in both object modeling and design methods and real-time scheduling theory is the key to successful use of object technology for real-time software. Surprisingly several past approaches to integrate the two either restrict the object models, or do not allow sophisticated schedulability analysis techniques. This study shows how schedulability analysis can be integrated with UML for Real-Time (UML-RT) to deal with timing properties in real time control systems. More specifically, we develop the schedulability and feasibility analysis modeling for the external messages that may suffer release jitter due to being dispatched by a tick driven scheduler in real-time control system and we also develop the scheduliablity modeling for sporadic activities, where messages arrive sporadically then execute periodically for some bounded time. This method can be used to cope with timing constraints in realistic and complex real-time control systems. Using this method, a designer can quickly evaluate the impact of various implementation decisions on schedulability. In conjunction with automatic code-generation, we believe that this will greatly streamline the design and development of real-time control systems software

TURTLE: Four Weddings and a Tutorial

The paper discusses an educational case study of protocol modelling in TURTLE, a real-time UML profile supported by the open source toolkit TTool. The method associated with TURTLE is step by step illustrated with the connection set up and handover procedures defined for the Future Air navigation Systems. The paper covers the following methodological stages: requirement modeling, use-case driven and scenario based analysis, object-oriented design and rapid prototyping in Java. Emphasis is laid on the formal verification of analysis and design diagrams

Modeling Networks-on-Chip at System Level with the MARTE UML profile

International audienceThe study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs