Two-run RAM march testing with address decimation

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator

Universal Signal Conditioning Amplifier

The Technological Research and Development Authority (TRDA) and NASA-KSC entered into a cooperative agreement in March of 1994 to achieve the utilization and commercialization of a technology development for benefiting both the Space Program and U.S. industry on a "dual-use basis". The technology involved in this transfer is a new, unique Universal Conditioning Amplifier (USCA) used in connection with various types of transducers. The project was initiated in partnership with I-Net Corporation, Lockheed Martin Telemetry & Instrumentation (formerly Loral Test and Information Systems) and Brevard Community College. The project consists of designing, miniaturizing, manufacturing, and testing an existing prototype of USCA that was developed for NASA-KSC by the I-Net Corporation. The USCA is a rugged and field-installable self (or remotely)- programmable amplifier that works in combination with a tag random access memory (RAM) attached to various types of transducers. This summary report comprises performance evaluations, TRDA partnership tasks, a project summary, project milestones and results

Implementation and Performance of Factorized Backprojection on Low-cost Commercial-Off-The-Shelf Hardware

Traditional Synthetic Aperture Radar (SAR) systems are large, complex, and expensive platforms that require significant resources to operate. The size and cost of the platforms limits the potential uses of SAR to strategic level intelligence gathering or large budget research efforts. The purpose of this thesis is to implement the factorized backprojection SAR image processing algorithm in the C++ programming language and test the code\u27s performance on a low cost, low size, weight, and power (SWAP) computer: a Raspberry Pi Model B. For a comparison of performance, a baseline implementation of filtered backprojection is adapted to C++ from pre-existing MATLAB® code. The factorized backprojection algorithm shows a computational improvement factor of 2-3 compared to filtered backprojection. Execution on a single Raspberry Pi is too slow for real-time imaging. However, factorized backprojection is easily parallelized, and we include a discussion of parallel implementation across multiple Pis

Analysis of Deep Learning Methods for Wired Ethernet Physical Layer Security of Operational Technology

The cybersecurity of power systems is jeopardized by the threat of spoofing and man-in-the-middle style attacks due to a lack of physical layer device authentication techniques for operational technology (OT) communication networks. OT networks cannot support the active probing cybersecurity methods that are popular in information technology (IT) networks. Furthermore, both active and passive scanning techniques are susceptible to medium access control (MAC) address spoofing when operating at Layer 2 of the Open Systems Interconnection (OSI) model. This thesis aims to analyze the role of deep learning in passively authenticating Ethernet devices by their communication signals. This method operates at the physical layer or Layer 1 of the OSI model. The security model collects signal data from Ethernet device transmissions, applies deep learning to gather distinguishing features from signal data, and uses these features to make an authentication decision on the Ethernet devices. The proposed approach is passive, automatic, and spoof-resistant. The role of deep learning is critical to the security model. This thesis will look at analyzing and improving deep learning at each step of the security model including data processing, model training, model efficiency, transfer learning on new devices, and device authentication

Digital radar receiver design based on highly efficient bandpass sampling FPGA architecture

Thesis (M.S.)--University of Oklahoma, 2009.Includes bibliographical references (leaves 62-64).As digital electronics become faster and more efficient, it becomes possible to move the analog/digital interface in a radar downconversion system further towards the antenna. Instead of digitizing radar echoes at the end of the down-conversion process, digital logic can perform the same operations previously performed by analog components. Taking full advantage of this opportunity will result in a more highly integrated and reconfigurable design. By removing unnecessary analog components, the error from component variability and noise injected into the signal of interest is reduced, the size of the receiver and the power required for operation is minimized, and the overall cost of the system can be lowered. This research is focused on employing software defined radio concepts for weather observation, thus creating a low-cost digital radar receiver at the University of Oklahoma for use in radar projects as a way of obviating the need for commmercial radar receivers, which can be many times more expensive. Software-defined radio techniques, such as bandpass sampling, are used to achieve a high data processing bandwidth and oversampling ratio with the smallest logic resource utilization. Two novel digital receiver designs are discussed in this thesis. A prototype compact single-channel digital receiver based on a 14-bit analog-to-digital converter and a hand-solderable Xilinx FPGA was built and tested both in the laboratory and at the National Weather Radar Testbed (NWRT). Building on the lessons learned from testing the single-channel digital radar receiver, a second digital receiver was designed for expanded capabilities. Through the utilization of a low-power, simultaneous-sampling eight channel ADC with high-speed serial data links and a cost-efficient FPGA with integrated DSP slices, eight data channels can be digitized, processed and transferred at the same time in a compact form factor. An ethernet interface has been included which allows for a scalable control channel so that the digital receiver's operations can be quickly modified. This also makes it possible to remotely change the firmware of the FPGA in seconds, without the need for physical access. Development of host computer platforms to store and process each digital receiver's output are also discussed

Development of a Flexible FPGA-Based Platform for Flight Control System Research

This work is part of ongoing research conducted at Virginia Commonwealth University relating to unmanned aerial vehicles. The primary objective of this thesis was to develop a flexible, high-performance autopilot platform in order to facilitate research on advanced flight control algorithms. A dual FPGA-based system architecture utilizing a stacked, multi-board design was created to meet this goal. Processing tasks were split between the two FPGA devices, allowing for improved system timing and increased throughput. A combination of analog and digital filtering techniques were employed in the new system, resulting in enhanced sensor accuracy and precision compared to the previous generation autopilot system. Several important improvements to the safety and reliability of the overall system were also achieved