High Gain Amplifier with Enhanced Cascoded Compensation

A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 μm technology, resulting, for a load of 45 pF and supply voltage of 1.65 V, in open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60o phase margin, 675 μW power consumption and 1% settling time of 28 ns

CMOS current amplifiers : speed versus nonlinearity

This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCII∞) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down. In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 μm CMOS-process. These filters use a differential CCII∞ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 μm BiCMOS-process, uses again a CCII∞. This circuit uses a pn-junction as a logarithmic feedback element. With a CCII∞ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 μm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe

Developing a framework of non-fatal occupational injury surveillance for risk control in palm oil mills

Non-fatal occupational injury (NFOI) and its risk factors have become a current global concern. The need of research towards the relationship between occupational injury and its risk factor is essential, to fulfil the purpose and setting the priority of implementing safety preventive approaches at workplace. This research intended to develop a framework of NFOI surveillance by using epidemiological data, noise exposure data and NFOI data among palm oil mills’ workers. A total of 420 respondents who assigned in operation and processing areas (OP) (n=333) and general or office workers (n=87) had voluntary participated in this research. A questionnaire session with respondents was held to obtain epidemiological data and NFOI information via validated questionnaire. Noise hazard monitoring was executed by using Sound Level Meter (SLM) for environmental noise monitoring and Personal Sound Dosimeter for personal noise monitoring. Gathered data were analysed in quantitative method by using statistical software IBM SPSS Statistic version 21 and a risk matrix table for injury risk rating evaluation. It was discovered that high noise exposure level (≥ 85 dB[A]) was significantly associated with non-fatal occupational injury among OP workers (φ=0.123, p<0.05) with OR=1.87 (95% CI, 1.080-3.235, p<0.05). Risk rating for reported NFOI was at moderate level, with minor cuts and scratches were the dominant type of injury (42.6%). Analysis of logistic regression indicated that working in shift, not wearing protective gloves, health problems such as shortness of breath and ringing in ears, and excessive noise level (≥ 85 dB[A]) were the risk factors of NFOI in palm oil mills among OP workers. A framework of nonfatal injury surveillance in palm oil mills was developed based on the findings with integration of risk management process and injury prevention principles. This framework is anticipated to help the management in decision making for preventive actions and early detection of occupational health effects among workers

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

Implicit feed-forward compensated op-amp with split pairs

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.Board of Regents, University of Texas Syste

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

CMOS OTA-C high-frequency sinusoidal oscillators

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3- and 2- mu m CMOS (MOSIS) prototypes that exhibit oscillation frequencies of up to 69 MHz are obtained. The amplitudes can be adjusted between 1 V peak to peak and 100 mV peak to peak. Total harmonic distortions from 2.8% down to 0.2% have been measured experimentally.Comisión Interministerial de Ciencia y Tecnología ME87-000

Novel CCII-based Field Programmable Analog Array and its Application to a Sixth-Order Butterworth LPF

In this paper, a field programmable analog array (FPAA) is proposed. The proposed FPAA consists of seven configurable analog blocks (CABs) arranged in a hexagonal lattice such that the CABs are directly connected to each other. This structure improves the overall frequency response of the chip by decreasing the parasitic capacitances in the signal path. The CABS of the FPAA is based on a novel fully differential digitally programmable current conveyor (DPCCII). The programmability of the DPCCII is achieved using digitally controlled three-bit MOS ladder current division network. No extra biasing circuit is required to generate specific analog control voltage signals. The DPCCII has constant standby power consumption, offset voltage, bandwidth and harmonic distortions over all its programming range. A sixth-order Butterworth tunable LPF suitable for WLAN/WiMAX receivers is realized on the proposed FPAA. The filter power consumption is 5.4mW from 1V supply; it’s cutoff frequency is tuned from 5.2 MHz to 16.9 MHz. All the circuits are realized using 90nm CMOS technology from TSMC. All simulations are carried out using Cadence

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current