Single Event Effects in CMOS Image Sensors

In this work, 3T Active Pixel Sensors (APS) are exposed to heavy ions (N, Ar, Kr, Xe), and Single Event Effects (SEE) are studied. Devices were fully functional during exposure, no Single Event Latch-up (SEL) or Single Event Functional Interrupt (SEFI) happened. However Single Event Transient (SET) effects happened on frames: line disturbances, and half or full circular clusters of white pixels. The collection of charges in cluster was investigated with arrays of two pixel width (7 and 10 \textmu{}m), with bulk and epitaxial substrates. This paper shows technological and design parameters involved in the transient events. It also shows that STARDUST simulation software can predict cluster obtained for bulk substrate devices. However, the discrepancies in epitaxial layer devices are large - which shows the need for an improved model

Development of generic testing strategies for mixed-signal integrated circuits

Describes work at the Polytechnic of Huddersfield SERC/DTI research project IED 2/1/2121 conducted in collaboration with GEC-Plessey Semiconductors, Wolfson Microelectronics, and UMIST. The aim of the work is to develop generic testing strategies for mixed-signal (mixed analogue and digital) integrated circuits. The paper proposes a test structure for mixed-signal ICs, and details the development of a test technique and fault model for the analogue circuit cells encountered in these devices. Results obtained during the evaluation of this technique in simulation are presented, and the ECAD facilities that have contributed to this and other such projects are described

Roadmap on semiconductor-cell biointerfaces.

This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world

Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations

Device modelling for bendable piezoelectric FET-based touch sensing system

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin)

Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)