Network-aware design-space exploration of a power-efficient embedded application

The paper presents the design and multi-parameter optimization of a networked embedded application for the health-care domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to optimize hardware requirements, packet loss, power consumption. Experimental results show that further power efficiency can be achieved by considering also communication aspects during design space exploratio

Virtual Platform-Based Design Space Exploration of Power-Efficient Distributed Embedded Applications

Networked embedded systems are essential building blocks of a broad variety of distributed applications ranging from agriculture to industrial automation to healthcare and more. These often require specific energy optimizations to increase the battery lifetime or to operate using energy harvested from the environment. Since a dominant portion of power consumption is determined and managed by software, the software development process must have access to the sophisticated power management mechanisms provided by state-of-the-art hardware platforms to achieve the best tradeoff between system availability and reactivity. Furthermore, internode communications must be considered to properly assess the energy consumption. This article describes a design flow based on a SystemC virtual platform including both accurate power models of the hardware components and a fast abstract model of the wireless network. The platform allows both model-driven design of the application and the exploration of power and network management alternatives. These can be evaluated in different network scenarios, allowing one to exploit power optimization strategies without requiring expensive field trials. The effectiveness of the approach is demonstrated via experiments on a wireless body area network application

Real-time VLSI architecture for bio-medical monitoring

This paper discusses the architecture and implementation of SSS2, a high-performance real-time signal processing system developed with a hybrid ESL/RTL methodology and targeted to biomedical image processing. Traditional methodologies, as well as new tools, such as Cebatech's C2R untimed-C synthesizer have been employed in the design of the system. The SSS2 platform specifies a parametric number of scalar processing elements, based on multiple 32-bit Sparc-compliant engines, augmented with LE2, an ESL-designed 2-way LIW/SIMD accelerator. LE2, which is purely designed in C, exposes a consistent interface to its SIMD datapath directly which is directly derived from the C-source of open-source image processing codes. It is synthesized to Verilog RTL with C2R. Behaviorally-synthesized SIMD datapaths are then 'plugged-in' into the exposed LE2 datapath interface. The LE2 memory interface can be either a cache- based configurable vector load/store unit or a multi-banked, multi-channel streaming local memory system. Results drawn from this work strongly suggest a shift towards a hybrid approach in designing multi-core systems for high bandwidth streaming and for dealing with large scale medical image transfers and non-linear bio-signal processing algorithms

Fast design space exploration of vibration-based energy harvesting wireless sensors

An energy-harvester-powered wireless sensor node is a complicated system with many design parameters. To investigate the various trade-offs among these parameters, it is desirable to explore the multi-dimensional design space quickly. However, due to the large number of parameters and costly simulation CPU times, it is often difficult or even impossible to explore the design space via simulation. This paper presents a response surface model (RSM) based technique for fast design space exploration of a complete wireless sensor node powered by a tunable energy harvester. As a proof of concept, a software toolkit has been developed which implements the proposed design flow and incorporates either real data or parametrized models of the vibration source, the energy harvester, tuning controller and wireless sensor node. Several test scenarios are considered, which illustrate how the proposed approach permits the designer to adjust a wide range of system parameters and evaluate the effect almost instantly but still with high accuracy. In the developed toolkit, the estimated CPU time of one RSM estimation is 25s and the average RSM estimation error is less than 16.5

A SystemC Simulator for Secure Data Transfer in Healthcare Internet of Things

In this thesis, a simulator for secure data transfer between medical sensors and end-users is developed using smart e-health gateways in medical environments like hospitals, healthcare centers and old-age homes. The rate of adoption of Internet of Things (IoT) and the associated technology is on the rise but the security measures that accompany the said technology and the devices is not totally dependable. And the repercussions get serious when dealing with medical sensors because people’s lives are at stake. With medical sensors, due to their resource and energy constraints, it is difficult to apply strong and heavy cryptographic techniques to achieve maximum security. The use of smart e-health gateways here eases the burden on sensors by authenticating and authorizing the end-users on behalf of the sensors. This is achieved using certificate-based DTLS handshake protocol between the gateways and the end-user. Then, for end-to-end secure communication, session resumption is carried out between the sensors and the end-users which is not as energy consuming as the handshake. The whole simulator is designed using SystemC, which is a library of C++ classes. It is chosen for this implementation because of various advantages it has over other hardware programming languages. SystemC, along with its verification library covers almost all aspects related to system design and modeling and the syntax of SystemC and C++ are the same. All the components of the hardware design are defined as modules here and the target is to achieve communication between these modules. Finally, we calculate the time it takes for a set of values to go from the sensor to the gateway and the gateway to the end-user

Performance analysis of 802.15.4 wireless standard

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