Study of interconnection networks /

A multi-stage N x N interconnection network is said to be universal if it realizes the set of all permutations on N objects. A new bound on the number of stages required for the universality of shuffle-exchange network as well as the analysis of the combinational power for the block-structured networks are given. Finally, the complexity of the verification of a new sufficient condition for rearrangeability due to Benes B5 is analyzed

Design of testbed and emulation tools

The research summarized was concerned with the design of testbed and emulation tools suitable to assist in projecting, with reasonable accuracy, the expected performance of highly concurrent computing systems on large, complete applications. Such testbed and emulation tools are intended for the eventual use of those exploring new concurrent system architectures and organizations, either as users or as designers of such systems. While a range of alternatives was considered, a software based set of hierarchical tools was chosen to provide maximum flexibility, to ease in moving to new computers as technology improves and to take advantage of the inherent reliability and availability of commercially available computing systems

Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs

A formalism for describing and simulating systems with interacting components.

This thesis addresses the problem of descriptive complexity presented by systems involving a high number of interacting components. It investigates the evaluation measure of performability and its application to such systems. A new description and simulation language, ICE and it's application to performability modelling is presented. ICE (Interacting ComponEnts) is based upon an earlier description language which was first proposed for defining reliability problems. ICE is declarative in style and has a limited number of keywords. The ethos in the development of the language has been to provide an intuitive formalism with a powerful descriptive space. The full syntax of the language is presented with discussion as to its philosophy. The implementation of a discrete event simulator using an ICE interface is described, with use being made of examples to illustrate the functionality of the code and the semantics of the language. Random numbers are used to provide the required stochastic behaviour within the simulator. The behaviour of an industry standard generator within the simulator and different methods of number allocation are shown. A new generator is proposed that is a development of a fast hardware shift register generator and is demonstrated to possess good statistical properties and operational speed. For the purpose of providing a rigorous description of the language and clarification of its semantics, a computational model is developed using the formalism of extended coloured Petri nets. This model also gives an indication of the language's descriptive power relative to that of a recognised and well developed technique. Some recognised temporal and structural problems of system event modelling are identified. and ICE solutions given. The growing research area of ATM communication networks is introduced and a sophisticated top down model of an ATM switch presented. This model is simulated and interesting results are given. A generic ICE framework for performability modelling is developed and demonstrated. This is considered as a positive contribution to the general field of performability research

The Design of a single chip 8x8 ATM switch in 0.5 micrometers CMOS VLSI

This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch using Very Large Scale Integration (VLSI). The ATM protocol is the data communications protocol used in the implementation of the Broadband Integrated Services Digital Network (B-ISDN), A number of switch architecture are first studied and a new architecture is developed based on optimizing performance and practicality of implementation in VLSI. A fully interconnected switch architecture is implemented by permanently connecting every input port to all the output ports. An output buffering scheme is used to handle cells that cannot be routed right away. This new architecture is caned the High Performance (HiPer) Switch Architecture. The performance of the architecture is simulated using a C++ model. Simulation results for a randomly distributed traffic pattern with a 90% probability of cells arriving in a time slot produces a Cell Loss Ratio of 1.Ox 10^-8 with output buffers that can hold 64 cells. The device is then modeled in VHDL to verify its functionality. Finally the layout of an 8x8 switch is produced using a 0.5 micrometer CMOS VLSI process and simulations of that circuit show that a peak throughput of 200 Mbps per output port can be achieve

Optical packet networking using optical time division multiplexing.

Growing demands for capacity have stimulated the development of high-speed optical shared media networks. At present, most research on optical networking has concentrated on wavelength-division multiplexing (WDM). Optical time-division multiplexing (OTDM), which offers advantages over WDM networks, is considered as an alternative to WDM for future networks proving a single stream data rates of 100 Gb/s using a single wavelength. In such systems all optical routers, which overcome the bottleneck of optoelectronic conversion, play an important role. This thesis concentrates on the modelling and simulation of a novel optical router, which uses two terahertz optical asymmetric demultiplexers (TOAD) as the routing element for OTDM systems.In this work, the author has developed a mathematical model of an all optical router based on TOADs. The model architecture is based on a system, which has as its input an OTDM packet containing header and payload information. The model simulates extraction of header information, using one TOAD, from the data stream, which is subsequently used to make a routing decision. The payload information is routed through a second TOAD according to the information contained in the header. A comprehensive theoretical analysis supported by computer simulations has been carried out to study characteristics of crosstalk, noises, signal to noise ratio (SNR), Bit error rate (BER), and power penalty of the router. The results obtained, whenever possible, have been compared with the experimented data.The performance analysis of the all optical router is shown by the simulation results. The proposed router is capable of routing packet containing data in excess of 250 Gb/s all in optical domain. New models of all optical router with multi-input and outputs have been developed i.e. 1x4 router, 2x2 router, which are based on 1x2 TOAD routers. Results show that threshold switching energy is present at 0.2 pJ. Higher values result in a decrease in crosstalk and lower values result in negligible switching. Also shown is crosstalk induced penalty depends on the crosstalk level of individual 1x2 switches as well as on the size and architecture of the switching fabric.Finally, it has been shown that the proposed all-optical router has potentially useful characteristics as a component for high-speed optical TDM networks due to its ultrafast switching capability compared with existing devices. At this stage a simple 8 by 8 Banyan network is presented, however further work will enhance the model to a network with more inputs and outputs

Solution of partial differential equations on vector and parallel computers

The present status of numerical methods for partial differential equations on vector and parallel computers was reviewed. The relevant aspects of these computers are discussed and a brief review of their development is included, with particular attention paid to those characteristics that influence algorithm selection. Both direct and iterative methods are given for elliptic equations as well as explicit and implicit methods for initial boundary value problems. The intent is to point out attractive methods as well as areas where this class of computer architecture cannot be fully utilized because of either hardware restrictions or the lack of adequate algorithms. Application areas utilizing these computers are briefly discussed