6 research outputs found
Agile Reactive Navigation for A Non-Holonomic Mobile Robot Using A Pixel Processor Array
This paper presents an agile reactive navigation strategy for driving a
non-holonomic ground vehicle around a preset course of gates in a cluttered
environment using a low-cost processor array sensor. This enables machine
vision tasks to be performed directly upon the sensor's image plane, rather
than using a separate general-purpose computer. We demonstrate a small ground
vehicle running through or avoiding multiple gates at high speed using minimal
computational resources. To achieve this, target tracking algorithms are
developed for the Pixel Processing Array and captured images are then processed
directly on the vision sensor acquiring target information for controlling the
ground vehicle. The algorithm can run at up to 2000 fps outdoors and 200fps at
indoor illumination levels. Conducting image processing at the sensor level
avoids the bottleneck of image transfer encountered in conventional sensors.
The real-time performance of on-board image processing and robustness is
validated through experiments. Experimental results demonstrate that the
algorithm's ability to enable a ground vehicle to navigate at an average speed
of 2.20 m/s for passing through multiple gates and 3.88 m/s for a 'slalom' task
in an environment featuring significant visual clutter.Comment: 7 page
Low power CMOS vision sensor for foreground segmentation
This thesis focuses on the design of a top-ranked algorithm for background
subtraction, the Pixel Adaptive Based Segmenter (PBAS), for its mapping onto a CMOS vision sensor on the focal
plane processing. The redesign of PBAS into its hardware oriented version, HO-PBAS, has led to a less number of
memories per pixel, along with a simpler overall model, yet, resulting in an acceptable loss of accuracy with respect
to its counterpart on CPU. This thesis features two CMOS vision sensors. The first one, HOPBAS1K, has laid out a
24 x 56 pixel array onto a miniasic chip in standard 180 nm CMOS technology. The second one, HOPBAS10K,
features an array of 98 x 98 pixels in standard 180 nm CMOS technology too. The second chip fixes some issues
found in the first chip, and provides good hardware and background performance metrics