Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

GaN-Based High Efficiency Transmitter for Multiple-Receiver Wireless Power Transfer

Wireless power transfer (WPT) has attracted great attention from industry and academia due to high charging flexibility. However, the efficiency of WPT is lower and the cost is higher than the wired power transfer approaches. Efforts including converter optimization, power delivery architecture improvement, and coils have been made to increase system efficiency.In this thesis, new power delivery architectures in the WPT of consumer electronics have been proposed to improve the overall system efficiency and increase the power density.First, a two-stage transmitter architecture is designed for a 100 W WPT system. After comparing with other topologies, the front-end ac-dc power factor correction (PFC) rectifier employs a totem-pole rectifier. A full bridge 6.78 MHz resonant inverter is designed for the subsequent stage. An impedance matching network provides constant transmitter coil current. The experimental results verify the high efficiency, high PF, and low total harmonic distortion (THD).Then, a single-stage transmitter is derived based on the verified two-stage structure. By integration of the PFC rectifier and full bridge inverter, two GaN FETs are saved and high efficiency is maintained. The integrated DCM operated PFC rectifier provides high PF and low THD. By adopting a control scheme, the transmitter coil current and power are regulated. A simple auxiliary circuit is employed to improve the light load efficiency. The experimental results verify the achievement of high efficiency.A closed-loop control scheme is implemented in the single-stage transmitter to supply multiple receivers simultaneously. With a controlled constant transmitter current, the system provides a smooth transition during dynamically load change. ZVS detection circuit is proposed to protect the transmitter from continuous hard switching operation. The control scheme is verified in the experiments.The multiple-reciever WPT system with the single-stage transmitter is investigated. The system operating range is discussed. The method of tracking optimum system efficiency is studied. The system control scheme and control procedure, targeting at providing a wide system operating range, robust operation and capability of tracking the optimized system efficiency, are proposed. Experiment results demonstrate the WPT system operation

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

On-chip adaptive power management for WPT-Enabled IoT

Internet of Things (IoT), as broadband network connecting every physical objects, is becoming more widely available in various industrial, medical, home and automotive applications. In such network, the physical devices, vehicles, medical assistance, and home appliances among others are supposed to be embedded by sensors, actuators, radio frequency (RF) antennas, memory, and microprocessors, such that these devices are able to exchange data and connect with other devices in the network. Among other IoT’s pillars, wireless sensor network (WSN) is one of the main parts comprising massive clusters of spatially distributed sensor nodes dedicated for sensing and monitoring environmental conditions. The lifetime of a WSN is greatly dependent on the lifetime of the small sensor nodes, which, in turn, is primarily dependent on energy availability within every sensor node. Predominantly, the main energy source for a sensor node is supplied by a small battery attached to it. In a large WSN with massive number of deployed sensor nodes, it becomes a challenge to replace the batteries of every single sensor node especially for sensor nodes deployed in harsh environments. Consequently, powering the sensor nodes becomes a key limiting issue, which poses important challenges for their practicality and cost. Therefore, in this thesis we propose enabling WSN, as the main pillar of IoT, by means of resonant inductive coupling (RIC) wireless power transfer (WPT). In order to enable efficient energy delivery at higher range, high quality factor RIC-WPT system is required in order to boost the magnetic flux generated at the transmitting coil. However, an adaptive front-end is essential for self-tuning the resonant tank against any mismatch in the components values, distance variation, and interference from close metallic objects. Consequently, the purpose of the thesis is to develop and design an adaptive efficient switch-mode front-end for self-tuning in WPT receivers in multiple receiver system. The thesis start by giving background about the IoT system and the technical bottleneck followed by the problem statement and thesis scope. Then, Chapter 2 provides detailed backgrounds about the RIC-WPT system. Specifically, Chapter 2 analyzes the characteristics of different compensation topologies in RIC-WPT followed by the implications of mistuning on efficiency and power transfer capability. Chapter 3 discusses the concept of switch-mode gyrators as a potential candidate for generic variable reactive element synthesis while different potential applications and design cases are provided. Chapter 4 proposes two different self-tuning control for WPT receivers that utilize switch-mode gyrators as variable reactive element synthesis. The performance aspects of control approaches are discussed and evaluated as well in Chapter 4. The development and exploration of more compact front-end for self-tuned WPT receiver is investigated in Chapter 5 by proposing a phase-controlled switched inductor converter. The operation and design details of different switch-mode phase-controlled topologies are given and evaluated in the same chapter. Finally, Chapter 6 provides the conclusions and highlight the contribution of the thesis, in addition to suggesting the related future research topics.Internet de las cosas (IoT), como red de banda ancha que interconecta cualquier cosa, se está estableciendo como una tecnología valiosa en varias aplicaciones industriales, médicas, domóticas y en el sector del automóvil. En dicha red, los dispositivos físicos, los vehículos, los sistemas de asistencia médica y los electrodomésticos, entre otros, incluyen sensores, actuadores, subsistemas de comunicación, memoria y microprocesadores, de modo que son capaces de intercambiar datos e interconectarse con otros elementos de la red. Entre otros pilares que posibilitan IoT, la red de sensores inalámbricos (WSN), que es una de las partes cruciales del sistema, está formada por un conjunto masivo de nodos de sensado distribuidos espacialmente, y dedicados a sensar y monitorizar las condiciones del contexto de las cosas interconectadas. El tiempo de vida útil de una red WSN depende estrechamente del tiempo de vida de los pequeños nodos sensores, los cuales, a su vez, dependen primordialmente de la disponibilidad de energía en cada nodo sensor. La fuente principal de energía para un nodo sensor suele ser una pequeña batería integrada en él. En una red WSN con muchos nodos y con una alta densidad, es un desafío el reemplazar las baterías de cada nodo sensor, especialmente en entornos hostiles, como puedan ser en escenarios de Industria 4.0. En consecuencia, la alimentación de los nodos sensores constituye uno de los cuellos de botella que limitan un despliegue masivo práctico y de bajo coste. A tenor de estas circunstancias, en esta tesis doctoral se propone habilitar las redes WSN, como pilar principal de sistemas IoT, mediante sistemas de transferencia inalámbrica de energía (WPT) basados en acoplamiento inductivo resonante (RIC). Con objeto de posibilitar el suministro eficiente de energía a mayores distancias, deben aumentarse los factores de calidad de los elementos inductivos resonantes del sistema RIC-WPT, especialmente con el propósito de aumentar el flujo magnético generado por el inductor transmisor de energía y su acoplamiento resonante en recepción. Sin embargo, dotar al cabezal electrónico que gestiona y condicionada el flujo de energía de capacidad adaptativa es esencial para conseguir la autosintonía automática del sistema acoplado y resonante RIC-WPT, que es muy propenso a la desintonía ante desajustes en los parámetros nominales de los componentes, variaciones de distancia entre transmisor y receptores, así como debido a la interferencia de objetos metálicos. Es por tanto el objetivo central de esta tesis doctoral el concebir, proponer, diseñar y validar un sistema de WPT para múltiples receptores que incluya funciones adaptativas de autosintonía mediante circuitos conmutados de alto rendimiento energético, y susceptible de ser integrado en un chip para el condicionamiento de energía en cada receptor de forma miniaturizada y desplegable de forma masiva. La tesis empieza proporcionando una revisión del estado del arte en sistemas de IoT destacando el reto tecnológico de la alimentación energética de los nodos sensores distribuidos y planteando así el foco de la tesis doctoral. El capítulo 2 sigue con una revisión crítica del statu quo de los sistemas de transferencia inalámbrica de energía RIC-WPT. Específicamente, el capítulo 2 analiza las características de diferentes estructuras circuitales de compensación en RIC-WPT seguido de una descripción crítica de las implicaciones de la desintonía en la eficiencia y la capacidad de transferencia energética del sistema. El capítulo 3 propone y explora el concepto de utilizar circuitos conmutados con función de girador como potenciales candidatos para la síntesis de propósito general de elementos reactivos variables sintonizables electrónicamente, incluyendo varias aplicaciones y casos de uso. El capítulo 4 propone dos alternativas para métodos y circuitos de control para la autosintonía de receptores de energíaPostprint (published version

Design of a CMOS RF Front End Receiver in 0.18μm Technology

An RF front end receiver system refers to the analog down conversion stages of the wireless communication system. The Digital base-band signals cannot be transmitted directly through wireless channels due to the properties of electromagnetic waves. The baseband signals need to be converted to analog through a digital-to-analog converter (DAC), up converted to higher frequency using an up conversion mixer and then transmitted through the channel. The received signals are down converted to base band frequency and then converted to digital again using the analog to digital converter (ADC). The processes which the analog signal undergoes at the RF front end include amplification, mixing and filtering. The RF Front End receiver developed in this thesis makes use of a differential low noise amplifier (LNA) with center frequency at 1.75GHz. The incoming RF signal undergoes amplification by the LNA and is down converted by a Gilbert double balanced mixer to a first Intermediate frequency (IF) of 250 MHz A second Gilbert Double Balanced Mixer down converts to a low second IF of 50 MHz The local oscillator signal for the mixer is generated using a voltage controlled ring oscillator (VCO). The entire front end of the receiver was created in Cadence virtuoso schematic editor using CMOS 0.18μm technology. The total power consumed by the RF Front End Receiver is 113.36 mW