Automated Synthesis of Memristor Crossbar Networks

The advancement of semiconductor device technology over the past decades has enabled the design of increasingly complex electrical and computational machines. Electronic design automation (EDA) has played a significant role in the design and implementation of transistor-based machines. However, as transistors move closer toward their physical limits, the speed-up provided by Moore\u27s law will grind to a halt. Once again, we find ourselves on the verge of a paradigm shift in the computational sciences as newer devices pave the way for novel approaches to computing. One of such devices is the memristor -- a resistor with non-volatile memory. Memristors can be used as junctional switches in crossbar circuits, which comprise of intersecting sets of vertical and horizontal nanowires. The major contribution of this dissertation lies in automating the design of such crossbar circuits -- doing a new kind of EDA for a new kind of computational machinery. In general, this dissertation attempts to answer the following questions: a. How can we synthesize crossbars for computing large Boolean formulas, up to 128-bit? b. How can we synthesize more compact crossbars for small Boolean formulas, up to 8-bit? c. For a given loop-free C program doing integer arithmetic, is it possible to synthesize an equivalent crossbar circuit? We have presented novel solutions to each of the above problems. Our new, proposed solutions resolve a number of significant bottlenecks in existing research, via the usage of innovative logic representation and artificial intelligence techniques. For large Boolean formulas (up to 128-bit), we have utilized Reduced Ordered Binary Decision Diagrams (ROBDDs) to automatically synthesize linearly growing crossbar circuits that compute them. This cutting edge approach towards flow-based computing has yielded state-of-the-art results. It is worth noting that this approach is scalable to n-bit Boolean formulas. We have made significant original contributions by leveraging artificial intelligence for automatic synthesis of compact crossbar circuits. This inventive method has been expanded to encompass crossbar networks with 1D1M (1-diode-1-memristor) switches, as well. The resultant circuits satisfy the tight constraints of the Feynman Grand Prize challenge and are able to perform 8-bit binary addition. A leading edge development for end-to-end computation with flow-based crossbars has been implemented, which involves methodical translation of loop-free C programs into crossbar circuits via automated synthesis. The original contributions described in this dissertation reflect the substantial progress we have made in the area of electronic design automation for synthesis of memristor crossbar networks

Reliability And Computing Techniques For Nano Switching Arrays

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2015Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2015Ticari ve uygulama yönü ele alındığında, yukarıdan aşağıya litografik entegre-devre üretimi limitine ulaşmaktadır. Moore Yasası'nın öngörüsü geçerliliğini sürdürse de yeni ortaya çıkan ve alternatif teknolojiler göz önünde bulundurulmalıdır. En güncel Yarıiletkenler için Uluslararası Teknoloji Yol Haritası raporlarında da belirtildiği gibi alternatif teknoloji arayışları devam etmektedir.  Özellikle nano boyuta inildiğinde ortaya çıkan sızıntı, hatalı üretimin yüksekliği gibi transistor sorunları, CMOS teknolojisinin üstesinden gelmesi gereken zorlukların en önemlileridir. Bahsedilen konular bu alanlarda çalışan araştırmacıları hesaplama, hafıza gibi devre yapılarında kullanılmak üzere farklı yaklaşımlar ve mimariler tasarlamaya itmiştir. CMOS teknolojisi göz önünde bulundurulduğunda yeni ortaya çıkan teknolojiler fiziksel açıdan CMOS'a benzer ve benzer olmayan şeklinde iki kategoriye ayrılabilir.  Fiziksel açıdan CMOS teknolojisine benzer yapılar, silikon nano-teller ve karbon nano-tüpler kullanarak devre elemanlarını üretir. Çalışmada odaklanılan ızgara tabanlı nano dizinler bu yaklaşımın bir örneğidir.  Fiziksel açıdan CMOS teknolojisine benzer olmayan yapılar, kuantum hücresel otomat, spintronik, tek elektron transistörleri, moleküler elektronik, DNA ve biyolojik hesaplamadır.  Yeni ortaya çıkan teknolojilerin üretim teknikleri, yukarıdan aşağıya veya aşağıdan yukarıya yaklaşımlar şeklinde iki ana kategori altında toplanabilir.  Yukarıdan aşağıya teknikler klasik litografi üretiminin iyileştirilmesi şeklinde ilerlemektedir ve marjinal fayda gün geçtikçe azalmaktadır.  Aşağıdan yukarıya teknikler ise devre elemanlarının tek başına üretilip daha sonra montajlanmasına dayanır. Bu yaklaşımın avantajı yüksek derecede düzenli yapılar oluşturmaya elverişli olmasına rağmen elde edilen elemanların geleneksel üretim paradigmasına göre yüksek düzeyde hatalı eleman içermesidir. Tezde odaklanılan teknoloji ızgara yapısına benzer nano anahtarlamalı dizinlerdir.   Araştırmacıların gösterdiği gibi ızgara şeklinde üst üste yerleştirilmiş nano-tellerin kesişim (jonksiyon) noktaları yarı iletkenlik özelliklerine göre direnç, diyot veya FET benzeri yapılar ortaya çıkarmıştır. Bu özellikten yararlanan ızgara tabanlı nano anahtarlamalı dizinler, CMOS teknolojisinin eksikliklerinin üstesinden gelmeye veya eksiklerini tamamlayıcı bir enstrüman olma konusunda olası bir adaydır. Literatürdeki çalışmaların yoğunluğu bu iddiayı destekler niteliktedir.  Nano dizinlerler hesaplama gerçekleştirmek için ortaya atılan farklı mimariler ayrıntılı bir şekilde incelenmiş, aralarında farklar ve benzerlikler yapıya özgü karakteristik özellikleri göz önünde bulundurularak açıklanmıştır. Teorik bir şekilde modellenmiş yapıların yanı sıra fiziksel olarak gerçeklenmiş işlemci ve sonlu durum makineleri de anlatılmıştır. Tezin gövdesini, bu ızgara yapıların lojik sentezinde ve hesaplamada kullanılması, lojik fonksiyonların girdilerinin dağılımlarının belirlenmesi ve yapıda oluşan hatalara rağmen lojik fonksiyonun verilen ızgara yapıyla gerçeklenmesi oluşturur. Ayrıca, üretim sürecinden sonra ortaya çıkan geçici hataların devre üzerindeki etkileri ve güvenilirlik analizi de göz önünde bulundurulmuştur.   Nano üretim doğası gereği rasgele süreçler içerir ve üretilen yapılar hatalı elemanlar içermeye yatkındır. Tezin odak noktası üretimde oluşan hatalar sonucu çalışmayan anahtarların sürece nasıl dahil edileceğidir. Hem nano-tellerin üretilmesi hem de istenilen yapıların oluşturulması için gerekli teknoloji oldukça pahalı ve zaman alıcı olduğundan son ürünün hatalı olması sonucu ıskartaya çıkması söz konusu değildir. Bu yüzden hatalı ürünlerin dolaşıma yeniden sokulması gerekir.  Üretim öncesi ve sonrası ortaya çıkan hatalar iki ana başlık altında incelenebilir: kalıcı ve geçici hatalar. Bu hata çeşitleri ayrıca üç alt başlığa ayrılır: açık-durumda takılı kalmış, kapalı-durumda takılı kalmış hatalar ve nano-tel kırılmaları. Nano-tel kırılmalarının devreye etkilerinin büyüklüğü yüzünden araştırmanın içeriğine dâhil edilmemiştir. Kalıcı hataların telafisi için sunulan algoritma lojik fonksiyonu ve hatalı nano-dizini incelemek için matris modelini kullanmaktadır. Algoritmanın amacı iki matris arasında bir eşleme bulmaktır. Algoritmanın yaralandığı buluşsal (\textit{Heuristic}) yaklaşımlar indeks sıralaması, geri-izleme ve tek tek eleman çarpımlı matris çarpımı teknikleridir.  İndeks sıralaması, lojik ve nano-dizin matrisine eşlenmesi gereken elemanların sayılarına göre satır ve sütun değişimleri uygular. Geri-izleme önceden eşlenmiş bölümlerin takibini ve yeniden eşlemeye sokulmasını düzenler. Tek tek eleman çarpımlı matris çarpımı iki matris arasında eşleme olup olmadığını ortaya çıkarır. Kalıcı hataların telafisi için izlenen yol, lojik sentez yaparken hatalardan kaçınılması veya hataların kullanılması şeklindedir. Bu çalışmada hatalar lojik sentez işlemine dahil edilmiş bir başka ifadeyle kullanılmıştır. Deneysel sonuçlar için anahtar görevi gören kesişim noktalarına rasgele hata atamaları yapılmıştır. Daha sonra standart bençmark devrelerinin, hatalı dizinle gerçeklenmesi veya gereçeklenememesi incelenmiştir.  Sunulan algoritma tüm olasılıkları göz önünde bulunduran kaba kuvvet algoritmasıyla karşılaştırıldığında  \%99 doğruluk oranı elde edilmiştir.  Ek olarak algoritmanın her bençmark fonksiyonu için ihtiyaç duyduğu çalışma süreleri de deneysel sonuçlar kısmında belirtilmiş ve diğer algoritmalarla karşılaştırmaları sunulmuştur. Üretim sonrası gerçekleştirilen lojik tasarım, hatalı yapıların yol açtığı bireysel düzenlemeden ötürü tasarım algoritmalarının koşma sürelerine verimlilik açısından yakından bağlıdır. Bu yüzden yüksek performansa sahip hızlı çalışma süreleri tasarım açısından göz ardı edilemeyecek önemdedir.    Geçici hatalar lojik fonksiyonun nano dizinle gerçeklenip üretilmesinden sonra ortaya çıktığı için hataların etkileri incelenmiştir. Açık-durumda takılı kalmış ve kapalı-durumda takılı kalmış hataların devreye olan etkileri farklıdır.  Açık-durumda takılı kalmış hatalar devrede bulunan girdiyi devre dışı bırakırken, kapalı-durumda takılı kalmış hatalar devreye yeni bir girdi eklemektedir. Çalışmada kullanılan lojik fonksiyonlar minimum formda yazıldığı için açık-durumda takılı kalmış hataların telafisi mümkün değildir. Herhangi bir girdinin devre dışı bırakılması minimum formda işlem yapıldığı için fonksiyondan alınan çıktıyı değiştirir.   Kapalı-durumda takılı kalmış hataların bazıları fonksiyonun karakterine göre telafi edilebilir. Nano dizinle elde edilmiş lojik fonksiyona denk fonksiyonların bulunması, telafi edilebilir hataların yerini göstermektedir. Çalışmada sunulan metot verilen bir lojik fonksiyona denk fonksiyonların cebirsel işlemlerle bulunmasının içerir. Bu şekilde telafi edilebilen hatalar belirlenmiş ve güvenilirlik analizi yapılmıştır.  Deneysel sonuçlar kısmında sunulan algoritmanın diğer algoritmalarla karşılaştırması verilmiş ve çalışma süreleri incelenmiştir. Ayrıca verilen lojik fonksiyonun gerçeklenmesi için verilen nano dizinin boyutunun algoritmanın çalışma süresine etkileri gösterilmiştir. Lojik fonksiyonun boyutundan daha büyük nano dizinlerle gerçeklemenin çalışma süresinin önemli seviyede etkilediği görülmüştür. Algoritmada sunulan sıralama yaklaşımının etkinliği yapılan benzetim sonuçlarıyla açıklanmıştır. Nano-dizin boyutunun algoritmanın çalışma süresi üzerindeki etkisi farklı boyutların göz önünde bulundurulmasıyla gösterilmiştir.Lithographic top-down based production of integrated circuits are approaching the limits in a manner of both feasibility and commercial aspects. In spite of the fact that, Moore's Law keeps holding, emerging technologies need to be considered. Crossbar based nano switching arrays are shown to be a likely candidate to overcome shortcomings of current CMOS based paradigm or coexist as a complementary instrument. Abundant research papers in literature help to support this claim. Nano-arrays are produced with placing a group of nanowires  aligned parallel to each other on another group of nanowires orthogonally. Crosspoints present between top and bottom nanowires act as a switching device. According to the preference, switches might show resistor, diode or FET like characteristics. Computing with nano-arrays are similar to the Programmable Logic Arrays (PLA). Every switch can be appointed to the corresponding logic element found in the boolean function which is realized with the crossbar in question. Nevertheless, the nature of nano-fabrication contains random elements and devices obtained from the process are prone to have faulty components. As a result, realization of target logic functions with nano-arrays differ from PLA due to the number of considerable faulty components.  Since discarding faulty devices would not be practical and sustainable, fault tolerance and reliability of crossbar based nano switching arrays are extensively studied in this thesis.  Most common faults occur in described switches can be categorized under two main titles which are permanent and transient. Also, two categories have subtitles such as stuck-open, stuck-closed and nanowire break-downs. Because of the immense effect of nanowire break-downs, they are excluded from the body of study.  Permanent faults are taken into account by independently assigning stuck-open and stuck-closed defect probabilities into crosspoints. After obtaining defective array, following step is determining whether there is a valid mapping of a given logic function on defective array. In the presence of permanent faults, a heuristic algorithm using index sorting, backtracking and matrix multiplication techniques is proposed. The algorithm’s effectiveness is demonstrated on standard benchmark circuits that shows 99\% accuracy in accordance with the results of an exhaustive search algorithm. Runtime and success rate of algorithm is presented with experimental results of simulation using standard industry benchmark circuits. In the presence of transient faults, tolerance analysis is performed by recursively constructing equivalent sets of implemented logic functions. It is demonstrated that transient faults causing OFF-to-ON state changes in crosspoints do not necessarily cause the array to produce an incorrect output; they can be discarded. Difference between the assumed and the actual fault tolerance performances, which is obtained with the proposed algebraic method, is presented with standard benchmark circuits for several fault rates.Yüksek LisansM.Sc

A survey of fault-tolerance algorithms for reconfigurable nano-crossbar arrays

ACM Comput. Surv. Volume 50, issue 6 (November 2017)Nano-crossbar arrays have emerged as a promising and viable technology to improve computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration with different technologies. However, certain problems need to be addressed, and the most important one is the prevailing occurrence of faults. Considering fault rate projections as high as 20% that is much higher than those of CMOS, it is fair to expect sophisticated fault-tolerance methods. The focus of this survey article is the assessment and evaluation of these methods and related algorithms applied in logic mapping and configuration processes. As a start, we concisely explain reconfigurable nano-crossbar arrays with their fault characteristics and models. Following that, we demonstrate configuration techniques of the arrays in the presence of permanent faults and elaborate on two main fault-tolerance methodologies, namely defect-unaware and defect-aware approaches, with a short review on advantages and disadvantages. For both methodologies, we present detailed experimental results of related algorithms regarding their strengths and weaknesses with a comprehensive yield, success rate and runtime analysis. Next, we overview fault-tolerance approaches for transient faults. As a conclusion, we overview the proposed algorithms with future directions and upcoming challenges.This work is supported by the EU-H2020-RISE project NANOxCOMP no 691178 and the TUBITAK-Career project no 113E760

A fast logic mapping algorithm for multiple-type-defect tolerance in reconfigurable nano-crossbar arrays

IEEE Transactions on Emerging Topics in Computing ( Early Access Journal article )Unlike conventional CMOS circuits, nano-crossbar arrays have considerably high defect rates. Multiple-type defects randomly occur both on crosspoint switches and wires that substantially complicates the design phase of the circuits with an elimination of systematic design choices. In order to overcome this problem, a logic mapping methodology is presented in this paper. A fast heuristic algorithm using pre-mapping logic morphing, defect oriented adaptive sorting, matching with Hadamard multiplication, and backtracking is introduced. The proposed algorithm covers both crosspoint defects including stuck-open and stuck-closed types and wire defects including bridging and broken types. Effects of stuck-closed defects, mostly disregarded in the literature, are studied in depth. In simulations, an industrial benchmark suit is used for obtaining runtime and success rate values of the proposed algorithm in comparison with those of the existing algorithms in the literature. A relative accuracy evaluation is also given in comparison with exact mapping techniques. Finally, the steps of the algorithm that are based on pre-mapping and heuristic matching techniques, are separately justified with experimental results.This work is supported by the EU-H2020-RISE project NANOxCOMP #691178 and the TUBITAK-Career project #113E760.Early access versio

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Permanent and transient fault tolerance for reconfigurable nano-crossbar arrays

This paper studies fault tolerance in switching reconfigurable nano-crossbar arrays. Both permanent and transient faults are taken into account by independently assigning stuck-open and stuck-closed fault probabilities into crosspoints. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. The algorithm's effectiveness is demonstrated on standard benchmark circuits in terms of runtime, success rate, and accuracy. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions. In this way, we are able to specify fault tolerance performances of nano-crossbars without relying on randomly generated faults that is relatively costly regarding that the number of fault distributions in a crossbar grows exponentially with the crossbar size.Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer project is supported by the EU-H2020-RISE project NANOxCOMP 691178 and the TUBITAK-CAREER project 113E760.Accepted for publicatio

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.Postprint (published version

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.This work is part of a project that has received funding from the European Union’s H2020 research and innovation programme under the Marie Skodowska-Curie grant agreement No 691178. This work is supported by the TUBITAK-Career project #113E76