Quantization Noise Shaping for Information Maximizing ADCs

ADCs sit at the interface of the analog and digital worlds and fundamentally determine what information is available in the digital domain for processing. This paper shows that a configurable ADC can be designed for signals with non constant information as a function of frequency such that within a fixed power budget the ADC maximizes the information in the converted signal by frequency shaping the quantization noise. Quantization noise shaping can be realized via loop filter design for a single channel delta sigma ADC and extended to common time and frequency interleaved multi channel structures. Results are presented for example wireline and wireless style channels.Comment: 4 pages, 6 figure

Asymmetrical digital subscriber line (ADSL) an in-depth study

Asymmetrical Digital Subscriber Line (ADSL) is one member of a group of broadband access technologies that uses the existing copper-based local loop of the analog PSTN for high-speed digital data transmission. One feature of ADSL is that it permits analog voice POTS transmissions to continue uninterrupted over the same wiring. Specifically, POTS continues to use the 0 to 4 KHz frequency range of the copper wiring, while ADSL uses bandwidth starting at 25 KHz and extending up to approximately 1.1 MHz for data transmission. The term asymmetrical refers to the fact that data rates downstream (to the user) and upstream (from the user) are not the same. Typical ADSL data rates range from 1.536 to 6.144 Mbps downstream and from 16 to 640 Kbps upstream. Local loop length, wire size, and the presence of devices to improve voice communication such as bridged taps and loading coils all affect ADSL data rates. Digital data is coded by one of two methods: Discrete Multitone Modulation (DMT) or Carrierless Amplitude and Phase Modulation (CAP). Echo control is also accomplished by one of two methods: Frequency Division Multiplexing (FDM) or echo cancellation. This paper consists of four sections: 1) A technical review and comparison of the CAP and DMT line encoding technologies. 2) A market review of the presence of CAP and DMT technologies in customer premise equipment (CPE) such as modems and routers. 3) A review of the POTS physical layer that exists between the ADSL subscriber and the Telco CO, and its impact on ADSL availability and quality of service (QOS). 4) A technical review of the newer, splitterless, G.Lite technolog

Time-Interleaved Analog-to-Digital Converter (TIADC) Compensation Using Multichannel Filters

Published methods that employ a filter bank for compensating the timing and bandwidth mismatches of an M-channel time-interleaved analog-to-digital converter (TIADC) were developed based on the fact that each sub-ADC channel is a downsampled version of the analog input. The output of each sub-ADC is filtered in such a way that, when all the filter outputs are summed, the aliasing components are minimized. If each channel of the filter bank has N coefficients, the optimization of the coefficients requires computing the inverse of an MN times MN matrix if the weighted least squares (WLS) technique is used as the optimization tool. In this paper, we present a multichannel filtering approach for TIADC mismatch compensation. We apply the generalized sampling theorem to directly estimate the ideal output of each sub-ADC using the outputs of all the sub-ADCs. If the WLS technique is used as the optimization tool, the dimension of the matrix to be inversed is N times N. For the same number of coefficients (and also the same spurious component performance given sufficient arithmetic precision), our technique is computationally less complex and more robust than the filter-bank approach. If mixed integer linear programming is used as the optimization tool to produce filters with coefficient values that are integer powers of two, our technique produces a saving in computing resources by a factor of approximately (100.2N(M- 1)/(M-1) in the TIADC filter design.published_or_final_versio

Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Constellation Shaping for WDM systems using 256QAM/1024QAM with Probabilistic Optimization

In this paper, probabilistic shaping is numerically and experimentally investigated for increasing the transmission reach of wavelength division multiplexed (WDM) optical communication system employing quadrature amplitude modulation (QAM). An optimized probability mass function (PMF) of the QAM symbols is first found from a modified Blahut-Arimoto algorithm for the optical channel. A turbo coded bit interleaved coded modulation system is then applied, which relies on many-to-one labeling to achieve the desired PMF, thereby achieving shaping gain. Pilot symbols at rate at most 2% are used for synchronization and equalization, making it possible to receive input constellations as large as 1024QAM. The system is evaluated experimentally on a 10 GBaud, 5 channels WDM setup. The maximum system reach is increased w.r.t. standard 1024QAM by 20% at input data rate of 4.65 bits/symbol and up to 75% at 5.46 bits/symbol. It is shown that rate adaptation does not require changing of the modulation format. The performance of the proposed 1024QAM shaped system is validated on all 5 channels of the WDM signal for selected distances and rates. Finally, it was shown via EXIT charts and BER analysis that iterative demapping, while generally beneficial to the system, is not a requirement for achieving the shaping gain.Comment: 10 pages, 12 figures, Journal of Lightwave Technology, 201

Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions